参数资料
型号: HY5PS12823F
英文描述: 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述: 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II内存- 512M
文件页数: 3/66页
文件大小: 862K
代理商: HY5PS12823F
Rev. 0.52/Nov. 02 3
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
KEY FEATURES Preliminary
VDD = 1.8V, 2.5V (Optional)
VDDQ = 1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable CAS latency 3, 4 and 5 supported
Programmable Additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4 / 8 with both nibble sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
Programmable tRAS supported
8K refresh cycles / 64ms
JEDEC standard 60ball FBGA(x4/x8) & 84bal FBGA(x16)l
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe supported (x8 only)
ORDERING INFORMATION
* X means speed grade
Part No.
Configuration
Package
HY5PS12423(L)F-X*
128Mx4
60 Ball
FBGA
HY5PS12823(L)F-X*
64Mx8
HY5PS121623(L)F -X*
32Mx16
84Ball
FBGA
OPERATING FREQUENCY
Grade
tCK(ns)
CL
tRCD
tRP
Unit
-D43
5
3
3
3
Clk
-D44
5
4
4
4
Clk
-D54
3.75
4
4
4
Clk
-D55
3.75
5
5
5
Clk
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