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| 型号： | HY5PS1G421LM |
| 厂商： | Hynix Semiconductor Inc. |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 1G DDR2内存（铂） |
| 文件页数： | 57/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G421LM |
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Rev. 0.2 / Oct. 2005
57
1
HY5PS12421(L)M
HY5PS12821(L)M
3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State
2
CKE
Command (N)
3
RAS, CAS, WE, CS
Action (N)
3
Notes
Previous Cycle
1
(N-1)
Current Cycle
1
(N)
Power Down
L
L
X
Maintain Power-Down
11, 13, 15
L
H
DESELECT or NOP
Power Down Exit
4, 8, 11,13
Self Refresh
L
L
X
Maintain Self Refresh
11, 15
L
H
DESELECT or NOP
Self Refresh Exit
4, 5,9
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down Entry
4,8,10,11,13
All Banks Idle
H
L
DESELECT or NOP
Precharge Power Down Entry
4, 8, 10,11,13
H
L
REFRESH
Self Refresh Entry
6, 9, 11,13
H
H
Refer to the Command Truth Table
7
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t
XSNR
period.
Read commands may be issued only after t
XSRD
(200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or
Precharge operations are in progress. See section 2.2.9 "Power Down" and 2.2.8 "Self Refresh Command" for a detailed list of
restrictions.
11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
section 2.2.2.4.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh
requirements outlined in section 2.2.7.
14. CKE must be maintained high while the SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or
low in Power Down if the ODT fucntion is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).
3.3 DM Truth Table
Name (Functional)
DM
DQs
Note
Write enable
L
Valid
1
Write inhibit
H
X
1
1. Used to mask write data, provided coinsident with the corresponding data
相关PDF资料 |
PDF描述 |
|---|---|
| HY5PS1G421LM-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421LM-E3 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-E3 | 1Gb DDR2 SDRAM(DDP) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G421LM-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421LM-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
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