参数资料
型号: HY5PS1G421M
厂商: Hynix Semiconductor Inc.
英文描述: 1Gb DDR2 SDRAM(DDP)
中文描述: 1G DDR2内存(铂)
文件页数: 20/79页
文件大小: 1109K
代理商: HY5PS1G421M
Rev. 0.2 / Oct. 2005
20
1
HY5PS12421(L)M
HY5PS12821(L)M
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the
following timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected
by
MRS addressing mode (ie. sequential or interleave).
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output
drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
1
0
1
0
Decrease by 1 step
Decrease by 1 step
Reserved
Other Combinations
NOP
NOP
NOP
NOP
EMRS
D
T0
CMD
CK
DQS_in
DQ_in
tDS
tDH
WL
OCD adjust mode
OCD calibration mode exit
D
T1
D
T2
D
T3
WR
EMRS
NOP
NOP
CK
DQS
DM
EMRS
NOP
NOP
NOP
EMRS
CMD
CK
DQS
DQS
DQ
Enter Drive mode
OCD calibration mode exit
tOIT
Hi-Z
DQs high for Drive(1)
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)
Hi-Z
DQs low for Drive(0)
tOIT
CK
相关PDF资料
PDF描述
HY5PS1G421M-C4 1Gb DDR2 SDRAM(DDP)
HY5PS1G421M-E3 1Gb DDR2 SDRAM(DDP)
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