- 您现在的位置：买卖IC网 > PDF目录384468 > HY5PS1G421M (Hynix Semiconductor Inc.) 1Gb DDR2 SDRAM(DDP) PDF资料下载
参数资料
| 型号： | HY5PS1G421M |
| 厂商： | Hynix Semiconductor Inc. |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 1G DDR2内存（铂） |
| 文件页数： | 38/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G421M |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页
Rev. 0.2 / Oct. 2005
38
1
HY5PS12421(L)M
HY5PS12821(L)M
2.6 Precharge Operation
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank independently or all banks simultaneously. Three
address bits A10, BA0 and BA1 for 512Mb are used to define which bank to precharge when the command is
issued.
Bank Selection for Precharge by Address Bits
Burst Read Operation Followed by Precharge
Minium Read to precharge command spacing to the same bank = AL + BL/2 clocks
For the earliest possible precharge, the precharge command may be issued on the rising edge which is
“Additive latency(AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to
the same bank after the RAS precharge time (t
RP
). A precharge command cannot be issued until t
RAS
is sat-
isfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock
egde that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to
Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge com-
mand. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.
A10
BA1
BA0
Precharged Bank(s)
Remarks
LOW
LOW
LOW
Bank 0 only
LOW
LOW
HIGH
Bank 1 only
LOW
HIGH
LOW
Bank 2 only
LOW
HIGH
HIGH
Bank 3 only
HIGH
DON’T CARE
DON’T CARE
All Banks
相关PDF资料 |
PDF描述 |
|---|---|
| HY5PS1G421M-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-E3 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821LM | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821LM-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY6264A-15 | RES 2.74 KOHM 1.0 % 2010S |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G421M-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G431AFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431AFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431ALFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
发布紧急采购，3分钟左右您将得到回复。