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参数资料
| 型号： | HY5V16CF-S |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16内存 |
| 文件页数： | 2/11页 |
| 文件大小： | 102K |
| 代理商： | HY5V16CF-S |
HY5V16CF
Rev. 0.0/Jun.01
2
PIN CONFIGURATION
(16M SDRAM)
PIN DESCRIPTION
PIN
P I N N A M E
D E S C R I P T I O N
C L K
C l o c k
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
C K E
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
C S
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
B A
Bank Address
Selects bank to be activated during R A S activity
Selects bank to be read/written during C A S activity
A 0 ~ A 1 0
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
R A S , C A S, W E
Row Address Strobe,
Column Address Strobe,
Write Enable
R A S , C A S and W E define the operation
Refer function truth table for details
L D Q M , U D Q M
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
D Q 0 ~ D Q 1 5
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuits and input buffers
V
D D Q
/V
S S Q
Data Output Power/Ground
Power supply for output buffers
N C
No Connection
No connection
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