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参数资料
| 型号： | HY628100BLT1-E |
| 厂商： | Hynix Semiconductor Inc. |
| 英文描述： | 128K x8 bit 5.0V Low Power CMOS slow SRAM |
| 中文描述： | 128K的x8位5.0V低功耗CMOS SRAM的速度 |
| 文件页数： | 7/10页 |
| 文件大小： | 175K |
| 代理商： | HY628100BLT1-E |
HY628100B Series
WRITE CYCLE 1(1,4,5,8) (/WE Controlled)
WRITE CYCLE 2 (Note 1,4,5,8) (/CS1, CS2 Controlled)
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and a high CS2.
2. tWR is measured from the earlier of /CS1 or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the the /CS1 low transition and CS2 high transition occur simultaneously with the /WE low transition
or after the /WE transition, outputs remain in a high impedance state.
6. Q(data out) is the same phase with the write data of this write cycle.
7. Q(data out) is the read data of the next address.
8. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
9. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev 12 / Apr.2001
6
Data Valid
ADDR
Data
Out
/CS1
CS2
/WE
tWC
tCW
tWR
(2)
tAW
tWP
Data In
High-Z
tAS
tWHZ
(3,7)
tDW
tDH
tOW
(
5
)
(
6
)
Data Valid
ADDR
Data
Out
/CS1
CS2
/WE
tWC
tCW
tWR
(2)
tAW
tWP
Data In
tDW
tDH
High-Z
High-Z
tAS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY628100BLT1-I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628100G-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| HY628100G-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| HY628100G-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| HY628100G-85 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
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