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参数资料
| 型号： | HYB39S256160TF-75 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | MEMORY SPECTRUM |
| 中文描述： | 记忆谱 |
| 文件页数： | 21/22页 |
| 文件大小： | 564K |
| 代理商： | HYB39S256160TF-75 |
INFINEON Technologies
8
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are
sampledonthe rising edge of theclock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiating either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS,RAS,and WE define the command to be executed by
the SDRAM.
A0 - A12
Input
Level
–
During a Bank Activate command cycle, A0-A12 define the
row address (RA0-RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-An define the
column address (CA0-CAn) when sampled at the rising
clock edge.CAn depends upon the SDRAM organization:
64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8 SDRAM
CAn = CA9
(Page Length = 1024 bits)
16M x16 SDRAM
CAn = CA8
(Page Length = 512 bits)
In addition to the column address, A10(= AP) is used to
invoke the autoprecharge operation at the end of the burst
read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged.
If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input
Level
–
Bank Select Inputs. Bank address inputs selects which of
the four banks a command applies to.
DQx
Input
Output
Level
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
相关PDF资料 |
PDF描述 |
|---|---|
| HYB39S256160TF-7F | MEMORY SPECTRUM |
| HYB39S256160TFL-37 | MEMORY SPECTRUM |
| HYB39S256160TFL-5 | MEMORY SPECTRUM |
| HYB39S256160TFL-7 | MEMORY SPECTRUM |
| HYB39S256160TFL-75 | MEMORY SPECTRUM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HYB39S256160TF-7F | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-3 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-37 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-5 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-7 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
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