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参数资料
| 型号： | HYB39S256160TF-75 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | MEMORY SPECTRUM |
| 中文描述： | 记忆谱 |
| 文件页数： | 5/22页 |
| 文件大小： | 564K |
| 代理商： | HYB39S256160TF-75 |
INFINEON Technologies
13
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
terminate once the burst length has been reached. In other words, unlike burst lengths of 2, 4 and
8, full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAMs, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations
are possible. With the programmed burst length, alternate access and precharge operations on two
or more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Burst Length and Sequence:
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the
CAS -before-RAS refresh of conventional DRAMs. All banks must be precharged before applying
any refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE
areheld highat a clock timing. Themoderestoreswordlineafter therefresh andnoexternal
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
Burst
Length
Starting Address
(A2 A1 A0)
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
012
34
56
7
123
45
67
0
234
56
70
1
345
67
01
2
456
70
12
3
567
01
23
4
670
12
34
5
701
23
45
6
01
23
456
7
10
32
547
6
23
01
674
5
32
10
765
4
45
67
012
3
54
76
103
2
67
45
230
1
76
54
321
0
Full
Page
nnn
Cn, Cn+1, Cn+2 ....
not supported
相关PDF资料 |
PDF描述 |
|---|---|
| HYB39S256160TF-7F | MEMORY SPECTRUM |
| HYB39S256160TFL-37 | MEMORY SPECTRUM |
| HYB39S256160TFL-5 | MEMORY SPECTRUM |
| HYB39S256160TFL-7 | MEMORY SPECTRUM |
| HYB39S256160TFL-75 | MEMORY SPECTRUM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HYB39S256160TF-7F | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-3 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-37 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-5 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TFL-7 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
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