- 您现在的位置：买卖IC网 > PDF目录224000 > HYMD264G726A4-H (HYNIX SEMICONDUCTOR INC) 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 PDF资料下载
参数资料
| 型号： | HYMD264G726A4-H |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封装： | 5.250 X 1.700 X 0.150 INCH, DIMM-184 |
| 文件页数： | 3/16页 |
| 文件大小： | 257K |
| 代理商： | HYMD264G726A4-H |
HYMD264G726A(L)4-M/K/H/L
Rev. 0.2/May. 02
11
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.
11
. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12.
I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.
13.
I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
14.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transi tions through the DC region must be monotonic.
15.
tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock
16.
For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
17.
tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
0.5
0
0.4
+75
0.3
+150
I/O Input Level
Delta tDS
Delta tDH
mV
ps
+280
+50
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
00
0
+/-0.25
+50
+/- 0.5
+100
相关PDF资料 |
PDF描述 |
|---|---|
| HYR164830G-653 | 48M X 16 RAMBUS MODULE, DMA84 |
| HYS64T16000HDL-2.5-A | 16M X 64 DDR DRAM MODULE, 0.4 ns, DMA200 |
| HYS72D64020GR-7-X | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| HYS72D64020GR-7.5-X | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| HYS72T128000EU-2.5-C2 | 128M X 72 DDR DRAM MODULE, 0.4 ns, DMA240 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HYMD264G726A4-K | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:Registered DDR SDRAM DIMM |
| HYMD264G726A4-L | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:Registered DDR SDRAM DIMM |
| HYMD264G726A4M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mx72|2.5V|M/K/H/L|x18|DDR SDRAM - Low Profile Registered DIMM 512MB |
| HYMD264G726A4-M | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:Registered DDR SDRAM DIMM |
| HYMD264G726A4M-H | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:Low Profile Registered DDR SDRAM DIMM |
发布紧急采购，3分钟左右您将得到回复。