参数资料
型号: I2042A-08ST
元件分类: 时钟及定时
英文描述: 2042 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封装: SOIC-8
文件页数: 2/8页
文件大小: 354K
代理商: I2042A-08ST
August 2005
P2042A
rev 1.3
Notice: The information in this document is subject to change without notice.
LCD Panel EMI Reduction IC
2 of 8
CP0
1
2
3
4
5
6
7
8
P2042A
CLKIN
CP1
VSS
SSON#
ModOUT
SR0
VDD
Pin Configuration
Pin Description
Pin#
Pin
Name
Type
Description
1
CLKIN
I
External reference frequency input. Connect to externally generated reference signal.
2
CP0
I
Digital logic input used to select charge pump current. This pin has an internal pull-up
resistor. Refer Modulation Selection Table.
3
CP1
I
Digital logic input used to select charge pump current. This pin has an internal pull-up
resistor. Refer Modulation Selection Table.
4
VSS
P
Ground to entire chip. Connect to system ground.
5
SSON#
I
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH.
This pin has an internal pull-low resistor.
6
ModOUT
O
Spread spectrum clock output.
7
SR0
I
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
8
VDD
P
Power supply for the entire chip
Modulation Selection
Spreading Range (±%)
CP0
CP1
SR0
32.5MHz
54MHz
65MHz
81MHz
108MHz
Modulation Rate
(KHz)
0
0.56
1.05
1.00
0.98
0.80
0
1
1.94
1.68
1.56
1.48
1.22
0
1
0
1.36
1.05
1.00
0.92
0.67
0
1
1.92
1.68
1.56
1.48
1.06
1
0
1.24
0.81
0.66
0.40
0.27
1
0
1
1.91
1.29
1.02
0.74
0.43
1
0
0.91
0.45
0.34
0.05
0.15
1
1.47
0.71
0.54
0.36
0.21
(FIN /40) * 62.49
KHz
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