参数资料
型号: I74F50729D-T
厂商: NXP SEMICONDUCTORS
元件分类: 锁存器
英文描述: F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封装: PLASTIC, SO-14
文件页数: 10/12页
文件大小: 104K
代理商: I74F50729D-T
Philips Semiconductors
Product data
74F50729
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
2003 Jan 20
7
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS1
MIN
TYP2
MAX
VOH
High-level output voltage
VCC = MIN, VIH = MIN
IOH = MAX
±10%V
CC
2.5
V
VIL = MAX,
±5%V
CC
2.7
3.4
V
IOH = –15 mA
±5%V
CC
2.0
V
VOL
Low-level output voltage
VCC = MIN, VIL = MAX,
IOL = MAX
±10%V
CC
0.30
0.50
V
VIH = MIN
±5%V
CC
0.30
0.50
V
VIK
Input clamp voltage
VCC = MIN, II = IIK
–0.73
–1.2
V
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0 V
100
A
IIH
High-level input current
VCC = MAX, VI = 2.7 V
20
A
IIL
Low-level input current
Dn
VCC = MAX, VI = 0.5 V
–250
A
CPn, SDn, RDn
–20
A
IOS
Short-circuit output current3
VCC = MAX, VO = 2.25 V
–60
–150
mA
ICC
Supply current4 (total)
VCC = MAX
19
27
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type
and function table for operating mode.
2. All typical values are at VCC = 5 V, Tamb = 25 °C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests.
In any sequence of parameter tests, IOS tests should be performed last.
4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
CONDITION
Tamb = +25 °C
Tamb = 0 °C to +70 °C
Tamb = –40 °C to +85 °C
VCC = +5.0 V
VCC = +5.0 V ± 10%
UNIT
CL = 50 pF,
RL = 500
CL = 50 pF,
RL = 500
CL = 50 pF,
RL = 500
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fmax
Maximum clock frequency
Waveform 1
105
120
85
75
ns
tPLH
tPHL
Propagation delay
CPn to Qn or Qn
Waveform 1
2.0
3.9
6.0
1.5
2.0
6.5
1.5
2.0
7.0
6.5
ns
tPLH
tPHL
Propagation delay
SDn RDn to Qn or Qn
Waveform 2
2.0
3.0
4.0
5.0
6.5
7.5
1.5
2.0
7.5
8.0
1.5
2.0
7.5
8.0
ns
tok(o)
Output skew1, 2
Waveform 4
1.5
ns
NOTES:
1. | tPLH actual –tPHL actual | for any one output compared to any other output where N and M are either LH or HL.
2. Skew lines are valid only under same conditions (temperature, VCC, loading, etc.).
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