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| 型号： | IA88C00-PLC68I-R-01 |
| 厂商： | Innovasic Semiconductor |
| 文件页数： | 26/80页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 20MHZ 68PLCC |
| 标准包装： | 285 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | EBI/EMI，UART/USART |
| 外围设备： | DMA，WDT |
| 输入/输出数： | 32 |
| 程序存储器类型： | 外部程序存储器 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 包装： | 管件 |
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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 32 of 80
1.888.824.4184
D5 WDT
The Watch-Dog Timer is initially enabled by writing a 1 to D5 and retriggered on subsequent writings to
the same bit. Reset value = 0. Writing a 0 to this bit has no effect. Once a 1 is written to D5, it persists
until a hardware reset occurs.
D6, D7 WDT Time-Out
Two sets of four different time-out values can be selected, depending on the logical state of these bits.
A normal reset signal must be active low during 5 XTAL clock periods. Using the reset signal input to
recover from STOP mode requires 10 XTAL clock periods. This is so that XTAL oscillation starts up and
stabilizes, generating a good oscillator output level.
The reset pin is held low in source during WDT timer time-out to accomplish a system reset with other
peripherals of the Super8. When the reset pin is held low, the capability of sink current via the reset pin
should be considered. (See DC Characteristics.)
Figure 29. UART Transmit Control (UTC), R235 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
0
1
0
Read/Write
R/W
This register cont ains the status and command bits needed to control the transmit sections of the UART.
0 - TDMAENB - Transmit DMA Enable - When this bit is set to 1, the DMA function for the UART
transmit section is enabled. If this bit is set and the Transmit Buffer Empty signal becomes true, a DMA
request is made. When the DMA channel gains control of the bus, it transfers bytes from the external
memory or the register file to the UART transmit section. A hardware reset forces this bit to 0.
D1 - TBE - Transmit Buffer Empty - This status bit is set to 1 whenever the transmit buffer is empty. It
is cleared to 0 when a data byte is written in the transmit buffer. A hardware reset forces this bit to 1.
D2 - ZC - Zero Count - This status bit is set to 1 and latched when the counter in the baud-rate generator
reaches the count of 0. This bit can be cleared to 0 by writing a 1 to this bit position. A hardware reset
forces this bit to 0.
D3 - TENB - Transmit Enable - Data is not transmitted until this bit is set to 1. When cleared to 0, the
Transmit Data pin continuously outputs 1s unless Auto-Echo mode is selected. This bit should be cleared
only after the desired transmission of data in the buffer is completed. A hardware reset forces this bit to 0.
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