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| 型号： | IA88C00-PLC68I-R |
| 厂商： | Innovasic Semiconductor |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件页数： | 59/80页 |
| 文件大小： | 707K |
| 代理商： | IA88C00-PLC68I-R |
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Copyright
2005 ENG21 1 030617-04 www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 59 of 80 1.888.824.4184
The IA88C00 also supports user-defined stacks. These stacks are accessed via the PUSHUI, POPUD,
LDEI and LDEPD instructions.
Counter/Timers
The IA88C00 provides two identical 16 bit timer/counters with an 8-bit prescaler. The counters are driven
from a divide-by-4 clock derived from the oscillator. Each count provides robust functionality including:
Up or down count
Single or continuous count
Output pulse train with variable duty cycle
Input capture
External gating/triggering
For longer events, the counters may be cascaded to form a 32-bit counter. For program model details see
registers R224 through R230.
DMA
The IA88C00 supports high speed data transfer support for the UART and handshake channel 0 via
Direct Memory Access (DMA). Data can be transferred between these peripherals and contiguous
locations in either the register file or external data memory. For details on the programming model see
registers R235 (UART transmit control) R236 (UART receive control), R244 (Handshake Channel 0
Control) and R240/241, Bank 1 (DMA Count).
WDT
The IA88C00 provides a “Watchdog” (WDT) timer to provide sanity checks on the processor. Should
program execution hang, the WDT timeout will expire and the RESET pin will be held active for 5 ms.
The WDT is prevented from timing out by periodically writing a “1” to bit D5 in the WDT/SMR register.
The WDT clock is derived from either an internal ring oscillator or from the crystal oscillator input. It
should be noted that the frequency of the internal oscillator and associated WDT time-out can vary widely
(as much as 3 times) with voltage and temperature. For details on the WDT programming model see
register R230 (WDT/SMR register).
Stop Mode
When a STOP instruction is executed, the process enter Stop Mode. During Stop mode, the system clock
and external oscillator are disabled. Stop Mode is exited via a hard reset, or by applying an edge to a pre-
defined bit of either Port 2, 3, or 4. For details on the Stop Mode programming model see register R230
(WDT/SMR register).
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