参数资料
型号: IA88C00
厂商: Innovasic Semiconductor
英文描述: Microcontroller
中文描述: 微控制器
文件页数: 31/80页
文件大小: 707K
代理商: IA88C00
IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Copyright
2005 ENG 21 0 050519-00 www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 31 of 80 1.888.824.4184
Figure 28b. Watch Dog Timer and Stop Mode Recovery Register (WDT/SMR) R230 Bank0
Bit
7
D7
6
D6
5
D5
WDT
Enable
0
R/W
4
D4
3
D3
WDT
Source
0
R/W
2
D2
SMR
On
0
R/W
1
D1
0
D0
WDT time-out
WDT in
Stop
0
R/W
SMR Source
Initial Value
Read/Write
This register controls the Watchdog Timer time-out and Stop recovery mode.
D1, D0 Stop Mode Recovery source select.
Bit D0 and D1 determine the Stop Mode Recovery source.
D1
D0
0
0
Recovery from RESET only
0
1
Recovery from P22 and RESET
1
0
Recovery from P32 and RESET
1
1
Recovery from any input for Port 4 and RESET
A hardware reset forces D0 and D1 to zero.
D2 Stop Recovery Edge
A 1 in this position indicates that a rising edge on any one of the recovery sources wakes the IA88C00
from Stop mode. A 0 indicates falling edge recovery. The reset value is 0.
D3 XTAL1/RC Select for WDT
When a zero is written to D3, the clock of the WDT is driven by the on-board RC oscillator. If D3 is set to
1, the WDT is driven by XTAL1. D3 has a zero reset value.
D4 WDT Enable During STOP or HALT
When this bit is set, WDT is enabled during STOP or HALT. In this case, recovery from STOP or HALT
should be performed before the selected time-out. A 0 in this bit location disables the WDT while the
IA88C00 is stopped or halted. A hardware reset forces this bit to a zero.
0
0
0
0
R/W
R/W
R/W
R/W
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