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参数资料
| 型号： | IBM25EMPPC750LFBE4000 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 7/50页 |
| 文件大小： | 600K |
| 代理商： | IBM25EMPPC750LFBE4000 |
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5/20/99
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
Page 11
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
AC Electrical Characteristics
This section provides the AC electrical characteristics for the 750. After fabrication, parts are sorted by maxi-
mum processor core frequency as shown in the Section “Clock AC Specifications,” on page 11, and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG(0-3) signals. Parts are sold by maximum proces-
sor core frequency; see Section “Ordering Information,” on page 45.
Clock AC Specications
The following table provides the clock AC timing specifications as defined in Figure 2.
Clock AC Timing Specications
See Table “Recommended Operating Conditions,” on page 7, for operating conditions.
Num
Characteristic
300MHz
333MHz
366MHz
400MHz
466MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Processor frequency
250
300
250
333
250
366
250
400
250
466
MHz
SYSCLK frequency
25
100
25
100
25
100
31
100
31
100
MHz
1
SYSCLK cycle time
10
40
10
40
12
40
10
32
10
32
ns
2,3
SYSCLK rise and fall
time
–
2.0
–
2.0
–
2.0
–
2.0
–
2.0
ns
2,3
4
SYSCLK duty cycle
measured at 1.4 V
40
60
40
60
40
60
40
60
40
60
%
3
SYSCLK jitter
–
±150
–
±150
–
±150
–
±150
–
±150
ps
4,3
Internal PLL relock
time
–
100
–
100
–
100
–
100
–
100
s5
Note:
1. Caution: The SYSCLK frequency and the PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, and CPU (core) fre-
quency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in Section “PLL Con-
figuration,” on page 35 for valid PLL_CFG[0-3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±150ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time
during the power-on reset sequence.
Figure 2. SYSCLK Input Timing Diagram
VM
CV
IL
CV
IH
1
2
4
3
4
SYSCLK
VM - Midpoint Voltage (1.4V)
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