参数资料
型号: IBM25PPC740-EB0M3000
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封装: 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件页数: 9/42页
文件大小: 496K
代理商: IBM25PPC740-EB0M3000
7/15/99
v 3.2
Datasheet
Page 17
Preliminary Copy
PowerPC 750TM SCM RISC Microprocessor
L2 Bus Input AC Specications
The L2 bus input interface AC timing specifications are found in Table 11.
Figure 14 shows the L2 bus input timing diagrams for the 750.
Table 11. L2 Bus Input Interface AC Timing Specications1
See Table 2 for operating conditions, L2OVDD = 3.3 ± 5% VDC or VDD
4
Num
Characteristic
Min
Max
Unit
Notes
29,30
L2SYNC_IN rise and fall time
1.0
ns
2,3
24
Data and parity input setup to L2SYNC_IN
1.7
ns
25
L2SYNC_IN to data and parity input hold
0.5
ns
Note:
1. All input specications are measured from the midpoint voltage (1.4V) of the signal in question to the midpoint voltage of
the rising edge of the input L2SYNC_IN. Input timings are measured at the pins (see Figure 14).
2. Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V.
3. Guaranteed by design and characterization, and not tested.
4. For SRAMs that can be operated at the VDD voltage, L2OVDD can also be tied to the VDD voltage.
Figure 14. L2 Bus Input Timing Diagrams
VM
VM = Midpoint Voltage (1.4V)
L2SYNC_IN
25
24
ALL INPUTS
29
30
VM
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