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| 型号： | IBM25PPC750GLECR5HA3T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 |
| 封装： | 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件页数： | 14/76页 |
| 文件大小： | 1031K |
| 代理商： | IBM25PPC750GLECR5HA3T |
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Datasheet
IBM PowerPC 750GL RISC Microprocessor
Preliminary
DD1.X
750GL_ds_body.fm 1.2
March 13, 2006
Electrical and Thermal Characteristics
Page 21 of 74
3.5 60x Bus Input AC Specifications
Table 3-8 provides the 60x bus AC timing specifications defined in Figure 3-4 and Figure 3-5 on page 23.
3.5.1 Input Setup Timing
The information in this subsection is provided to clarify the criteria used to establish the timings in Table 3-8.
The DC Electrical Specifications shown in Table 3-4 on page 16 are not altered by this clarification. The valid
input signal levels remain VIH and VIL.
The input setup times shown as 10a in Table 3-8 specify the required time from the input signal crossing VM
to the rising edge of SYSCLK crossing VM.
For the timings in Table 3-8 to be valid, the falling edge of the input signal shown in Table 3-8 is assumed to
transition through VM and cross VIL-AC at the slew rate specified in Table 3-8. Input signals that do not reach
the VIL-AC boundary, or slew from VM to VIL-AC more slowly than specified, will result in longer input setup
times.
In the same way, on the rising edge, the input signal must continue past VM and cross the VIH-AC boundary
within the specified minimum slew rate. Input signals that do not reach the VIH-AC boundary within the slew
rate specified will result in longer input setup times.
Figure 3-4 provides the input timing diagram for the 750GL.
Table 3-8. 60x Bus Input AC Timing Specifications
See Table 3-2 on page 15 for operating conditions.1, 5, 6
Figure 3-4
and 3-5
Timing
Reference
Characteristic
1.8 V Mode
2.5 V Mode
3.3 V Mode
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
10a
Input setup: SYSCLK to inputs valid.
1.0
—
1.1
—
1.6
—
ns
10c
Mode select input setup to HRESET (TLBI-
SYNC, DRTRY, L2_TSTCLK, DBDIS,
QACK, and DBWO)
8—
8—8—
tSYSCLK
11a
Input hold: SYSCLK to inputs invalid, SMI,
TBEN, DRTRY, INT, MCP, and TLBISYNC
0.45
—
0.3
—
0.3
—
ns
11c
HRESET to mode select input hold (TLBI-
SYNC, DRTRY, L2_TSTCLK, DBDIS,
QACK, and DBWO)
0—
0—0—
ns
VM
Measurement reference voltage for inputs
OVDD/2
—
VIL-AC
AC timing reference levels
—0.2
VIH-AC
OVDD - 0.2
—OVDD - 0.2
—
Slew Rate Reference input slew rate
1.0
—
1.5
—
2.0
—
V/ns
Notes:
1. Input specifications are measured from the midpoint voltage (VM) of the signal in question to the VM of the rising edge of the input
SYSCLK. Timings are measured at the pin (see Figure 3-4 on page 22).
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-5 on page 23).
3. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the
period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
5. All values are guaranteed by design, and are not tested.
6. Refer to Section 3.5.1 on page 21 and Figure 3-3 on page 22 for input setup timing definitions.
7. Input reference signal levels used to establish the timings defined in this table.
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| IBM25PPC750GLECR5HB3T | 制造商:IBM 功能描述:IBMIBM25PPC750GLECR5HB3T LOGIC POWER PC 制造商:IBM 功能描述:32 BIT MPU - Trays |
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