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| 型号： | IBM25PPC750GLECR5HA3T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 |
| 封装： | 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件页数： | 17/76页 |
| 文件大小： | 1031K |
| 代理商： | IBM25PPC750GLECR5HA3T |
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Datasheet
IBM PowerPC 750GL RISC Microprocessor
DD1.X
Preliminary
Electrical and Thermal Characteristics
Page 24 of 74
750GL_ds_body.fm 1.2
March 13, 2006
3.6 60x Bus Output AC Specifications
Table 3-9 provides the 60× bus output AC timing specifications for the 750GL as defined in Figure 3-7 on
Table 3-9. 60x Bus Output AC Timing Specifications
See Table 3-2 on page 15 for operating conditions.1, 4, 6
Figure 3-7
Timing
Reference
Characteristic
1.8 V
2.5 V
3.3 V
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
12
SYSCLK to Output Driven
(Output Enable Time)
0.3
—
0.3
—
0.3
—
ns
13
SYSCLK to Output Valid
—
2.4
—
2.3
—
2.4
ns
14
SYSCLK to Output Invalid (Output Hold)
1.0
—
0.6
—
0.6
–
ns
15
SYSCLK to Output High Impedance
(all signals except address retry [ARTRY],
address bus busy [ABB], and data bus
busy [DBB])
—2.5
—
2.5
ns
16
SYSCLK to ABB and DBB high impedance
after precharge
—1.0
—
1.0
tSYSCLK
17
SYSCLK to ARTRY high impedance
before precharge
—3.0
—
3.0
ns
18
SYSCLK to ARTRY precharge enable
0.2
×
tSYSCLK +
1.0
0.2
×
tSYSCLK +
1.0
—
0.2
×
tSYSCLK +
1.0
—ns
19
Maximum delay to ARTRY precharge
—
1.0
—
1.0
—
1.0
tSYSCLK
20
SYSCLK to ARTRY high impedance
after precharge
—2.0
—
2.0
tSYSCLK
Notes:
1. All output specifications are measured from the VM of the rising edge of SYSCLK to the midpoint of the output signal in question
using a test load as shown in Figure 3-6 on page 25. Both input and output timings are measured at the pin. Timings are deter-
mined by design.
2. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration of the parameter in question.
3. Nominal precharge width for ARTRY is 1.0 tSYSCLK.
4. Guaranteed by design and characterization, and not tested.
5. Output Valid timing increases as the VDD is reduced. These values assume a VDD minimum of 1.4 V.
6. See Figure 3-6 on page 25 and Figure 3-7 on page 26 for output loading and timing definitions.
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| IBM25PPC750GLECR5HB3T | 制造商:IBM 功能描述:IBMIBM25PPC750GLECR5HB3T LOGIC POWER PC 制造商:IBM 功能描述:32 BIT MPU - Trays |
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