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参数资料
| 型号： | IBM25PPC750L-FB0A466W |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 14/46页 |
| 文件大小： | 610K |
| 代理商： | IBM25PPC750L-FB0A466W |
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9/30/99
Version 2.0
Datasheet
Page 17
PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
L2 Bus Input AC Specications
The L2 bus input interface AC timing specifications are found in the following table.
Figure 7 shows the L2 bus input timing diagrams for the PID8p-750.
L2 Bus Input Interface AC Timing Specications
See Table “Recommended Operating Conditions1,2,3,” on page 6, for operating conditions.
Num
Characteristic
Min
Max
Unit
Notes
29,30
L2SYNC_IN rise and fall time
—
1.0
ns
2,3
24
Data and parity input setup to L2SYNC_IN; processor core at
or below 375 MHz
1.5
—
ns
1
24
Data and parity input setup to L2SYNC_IN; processor core at
400 MHz
1.4
—
ns
1
24
Data and parity input setup to L2SYNC_IN; processor core at
433, 450MHz
1.1
—
ns
1
24
Data and parity input setup to L2SYNC_IN; processor core at
466, 500MHz
1.0
—
ns
1
25
L2SYNC_IN to data and parity input hold
0.5
—
ns
1
Note:
1. All input specifications are measured from the midpoint voltage of the signal in question to the midpoint voltage of the rising edge of the input
L2SYNC_IN. Input timings are measured at the pins (see Figure 7). Midpoint voltage (VM) is 1.4v for (2OVdd) in 3.3v and (2OVdd/2) for all other IO
modes .
2. Rise and fall times for the L2SYNC_IN input are measured from 0.5 to 1.5v.
3. Guaranteed by design and characterization, and not tested.
Figure 7. L2 Bus Input Timing Diagrams
VM
VM = Midpoint voltage is 1.4v for (2OVdd) in 3.3v
L2SYNC_IN
25
24
ALL INPUTS
29
30
VM
and (2OVdd/2) for all other I/O modes
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|---|---|
| IBM25PPC750L-FB0B300W | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-Bit Microprocessor |
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