IBM39STB0210x
Advance
STB0210x Digital Set-Top Box Integrated Controllers
STB02_sds_0327.fm.01
March 27, 2000
Pin and I/O Information
Page 29 of 39
General Purpose I/O (GPIO)
The following table describes the GPIO bits. For each GPIO bit only one signal can be selected at a time.
Each table row lists the signal associated with each logical GPIO bit number. The rst column lists the
GPIO bit number. The second column lists the signal connected as input or output to the rst alternate
GPIO multiplexer. The signal name is listed rst, followed by the signal description. The third column
gives the direction of the signal listed in column 2. The same format is used for columns 4 through 7.
Blank entries indicate reserved GPIO multiplexing.
GPIO bit number refers to the device GPIO signal name, not the physical device pin number.
After reset all GPIOs are programmed as inputs, with the exception of GPIO0 bit 29 (PWM output),
which defaults to an open-drain output, and GPIO bit 14 (JTAG TDO output), which defaults to an output
(if BI_DATA[4] is set to ‘0’ during reset).
General Purpose I/O Bits
Bit #
Input/Output Mux 1
Type
Input/Output Mux 2
Type
Input/Output Mux 3
Type
00
01
02
AV_CSYNC
BI_CS4
I
O
GPT_FreqGenOut
O
INT4
I
03
SYS_CLK
O
BI_CS5
O
INT5
I
04
EDMAC0_REQ
I
SD1_CS1
O
SERIAL0/16550_DTR
O
05
EDMAC0_ACK
O
SERIAL0/16550_DSR
I
06
SCP_TXD
O
CI_PACKET_START
I
SERIAL0/16550_DCD
I
07
SCP_RXD
I
CI_DATA_ERROR
I
TS_BCLKEN
I
08
SCP_CLK
O
TS_REQ
O
SERIAL0/16550_RI
I
09
PWM0
O
GPT_COMP0
O
GPT_CAPT0
BI_CS6
I
O
10
PWM1
O
GPT_COMP1
O
GPT_CAPT1
BI_CS7
I
O
11
RW_TMS
I
SSP_TXD
O
BI_CS6
O
12
RW_TDI
I
SSP_RXD
I
BI_CS7
O
13
RW_TCK
I
SSP_CLK
I
INT6
I
14
RW_TDO
O
SSP_FS
I/O
INT7
I
15
RW_HALT
I
SERIAL0/16550_CLK - External
SERIAL0/16550 Clock Input
I
SYS_CLK
O
16
BI_CS4
O
17
BI_CS5
O
HSP_ERROR
O
18
DV_TRANSPARENCY_
GATE
I/O
DV2_PIXEL_CLOCK
I
SERIAL1/INFRARED_CLK -
External SERIAL1/INFRARED
Clock Input
I
19
TTX_REQ
I/O
DV2_VSYNC
I/O