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参数资料
| 型号： | IBM39STB02101PBA22C |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 36/39页 |
| 文件大小： | 503K |
| 代理商： | IBM39STB02101PBA22C |
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IBM39STB0210x
Advance
STB0210x Digital Set-Top Box Integrated Controllers
STB02_sds_0327.fm.01
March 27, 2000
Architecture and Subsystem Information
Page 6 of 39
On-chip instruction is compatible with PowerPC User Instruction Set Architecture. There are 32 x 32 bit gen-
eral purpose registers. Instruction and data cache arrays improve system throughput. The CPU has a sepa-
rate two-way set-associative 16KB instruction cache and an 8KB write-back/write-through data cache.
Multiply and divide instructions are performed in hardware and are not emulated in software.
Universal Interrupt Controller
The Universal Interrupt Controller (UIC) provides all necessary control, status, and communication functions
between all sources of interrupts and the PPC401B3. The UIC combines STB0210x interrupts and presents
them to the PPC401B3’s critical or non-critical inputs. All interrupts can be programmed to generate either
critical or non-critical output. Interrupts can be level- or edge-sensitive and interrupt polarity is programmable.
An optional read-only vector is used to reduce critical interrupt servicing latency. This vector is generated by
combining an offset (based on the bit position of the highest priority, enabled, and active critical interrupt) and
a vector base address register. A configurable priority control bit determines whether the least significant or
most significant bit in the status register has the highest priority.
Clock and Power Management
For power-saving purposes, a Clock and Power Management (CPM) input is used to shut down clocks and
device functions. A reset is required to activate a unit.
Memory Interface Subsystem
The memory interface subsystem provides the system memory controller interface for SRAM, FLASH Mem-
ory, ROM, and SDRAM. It also provides the Direct Memory Access (DMA) interfaces for these memories.
Direct Memory Access Controller
The four-channel DMA controller is a processor local bus master that allows faster data transfer between
memory and peripherals than with program control. The controller supports memory-to-memory, peripheral-
to-memory, and memory-to-peripheral transfers. The DMA controller allows the PPC401B3 processor to exe-
cute instructions with no bus contention when the PPC401B3 is executing from cache. DMA is useful when
the overhead associated with the controller setup is minimal compared to the time it would take to move data
using program control load and store instructions.
Memory Subsystem
PLB1
PLB0
DMA
SDRAM1
SDRAM
Crossbar
EBIU
FLASH,
ROM, etc.
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