参数资料
型号: IC41C82052
英文描述: 2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
中文描述: 200万× 8(16兆),充满活力和快速页面模式内存
文件页数: 14/18页
文件大小: 196K
代理商: IC41C82052
IC41C82052
IC41LV82052
Integrated Circuit Solution Inc.
5
DR015-0A 06/12/2001
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
Max.
Unit
IIL
Input Leakage Current
Any input 0V < VIN < Vcc
5
A
Other inputs not under test = 0V
IIO
Output Leakage Current
Output is disabled (Hi-Z)
5
A
0V < VOUT < Vcc
VOH
Output High Voltage Level
IOH = 5.0 mA with VCC=5V
2.4
V
IOH = 2.0 mA with VCC=3.3V
VOL
Output Low Voltage Level
IOL = 4.2 mA with VCC=5V
0.4
V
IOL = 2 mA with VCC=3.3V
ICC1
Standby Current: TTL
RAS, CAS > VIH
5V
2
mA
3.3V
0.5
ICC2
Standby Current: CMOS
RAS, CAS > VCC 0.2V
5V
1
mA
3.3V
0.5
ICC3
Operating Current:
RAS, CAS,
-50
120
mA
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
-60
110
Average Power Supply Current
ICC4
Operating Current:
RAS = VIL, CAS,
-50
90
mA
.ast Page Mode(2,3,4)
tRC = tRC (min.)
-60
80
Average Power Supply Current
ICC5
Refresh Current:
RAS Cycling, CAS > VIH
-50
120
mA
RAS-Only(2,3)
tRC = tRC (min.)
-60
110
Average Power Supply Current
ICC6
Refresh Current:
RAS, CAS Cycling
-50
120
mA
CBR(2,3,5)
tRC = tRC (min.)
-60
110
Average Power Supply Current
Notes:
1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tRE. refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
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