参数资料
型号: ICL7135CPI
厂商: Intersil
文件页数: 10/15页
文件大小: 0K
描述: IC CONV A/D 4 1/2 DIGIT 28-DIP
标准包装: 13
系列: *
其它名称: ICL7135CPIIS
NT5015
ICL7135
POL
+5V
HI VOLTAGE BUFFER D1 505
A
G
47K
A
G
RBI
V +
DM
8880
RB0 PROG
BI D A
+5
3K
0V
This shift occurs during the reference integrate phase of
conversion causing a low display reading just after overrange
recovery. Both of the above circuits have considerable current
flowing in the digital supply from drivers, etc. A clock source
using an LM311 voltage comparator with positive feedback
(Figure 11) could minimize any clock frequency shift problem.
5K
2.5K
GATES
ARE
7409
0.02 μ F
0.02 μ F
The ICL7135 is designed to work from ± 5V supplies.
However, if a negative supply is not available, it can be
generated with an ICL7660 and two capacitors (Figure 12).
Interfacing with UARTs and
Microprocessors
POL D5
ICL7135
D1
B8
B1
V+
DGND
+5
0V
Figure 13 shows a very simple interface between a free-running
ICL7135 and a UART. The five STROBE pulses start the
transmission of the five data words. The digit 5 word is
0000XXXX, digit 4 is 1000XXXX, digit 3 is 0100XXXX, etc. Also
the polarity is transmitted indirectly by using it to drive the Even
FIGURE 8. ICL7135 PLASMA DISPLAY CIRCUIT
Parity Enable Pin (EPE). If EPE of the receiver is held low, a
parity flag at the receiver can be decoded as a positive signal,
+5V
BP
4 1 / 2 DIGIT LCD DISPLAY
no flag as negative. A complex arrangement is shown in Figure
14. Here the UART can instruct the A/D to begin a
measurement sequence by a word on RRl. The BUSY signal
resets the Data Ready Reset (DRR). Again STROBE starts the
transmit sequence. A quad 2 input multiplexer is used to
23 POL
1 / 2 CD4030
superimpose polarity, over-range, and under-range onto the D5
20 D1
19 D2
18 D3
17 D4
16 B8
15 B4
14 B2
13 B1
12 D5
26 STROBE
27 OR
ICL7135
CD4081
CD4071
1/4 CD4030
5 BP
31 D1
32 D2
33 D3
34 D4
30 B3
29 B2
28 B1
27 B0
CD4011 ICM7211A
word since in this instance it is known that B2 = B4 = B8 = 0.
For correct operation it is important that the UART clock be fast
enough that each word is transmitted before the next STROBE
pulse arrives. Parity is locked into the UART at load time but
does not change in this connection during an output stream.
Circuits to interface the ICL7135 directly with three popular
microprocessors are shown in Figure 15 and Figure 16. The
8080/8048 and the MC6800 groups with 8-bit buses need to
have polarity, over-range and under-range multiplexed onto
the Digit 5 Sword - as in the UART circuit. In each case the
microprocessor can instruct the A/D when to begin a
measurement and when to hold this measurement.
Application Notes
NOTE #
DESCRIPTION
AN016
Selecting A/D Converters
AN017
The Integrating A/D Converter
+5V
1 / 4 CD4030
AN018
Do’s and Don’ts of Applying A/D Converters
FIGURE 9. LCD DISPLAY WITH DIGIT BLANKING ON
OVERRANGE
A problem sometimes encountered with both LED and plasma-
type display driving is that of clock source supply line variations.
Since the supply is shared with the display, any variation in
voltage due to the display reading may cause clock supply
voltage modulation. When in overrange the display alternates
between a blank display and the 0000 overrange indication.
10
AN023
AN028
AN054
AN9510
AN9609
Low Cost Digital Panel Meter Designs
Building an Auto-Ranging DMM Using the 8052A/7103A
A/D Converter Pair
Display Driver Family Combines Convenience of Use
with Microprocessor Interfaceability
Basic Analog for Digital Designers
Overcoming Common Mode Range Issues When Using
Intersil Integrating Converters
FN3093.4
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