参数资料
型号: ICM7216DIPI
厂商: Intersil
文件页数: 18/18页
文件大小: 0K
描述: IC COUNTER/TIMER FREQ 8DIG 28DIP
标准包装: 78
系列: *
其它名称: 7216DIPI
NT5007
ICM7216B, ICM7216D
Dual-In-Line Plastic Packages (PDIP)
N
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INDEX
AREA
1 2 3
N/2
E1
-B-
SYMBOL
A
INCHES
MIN MAX
-
0.250
MILLIMETERS
MIN MAX
-
6.35
NOTES
4
-A-
BASE
D
E
A1
A2
0.015
0.125
-
0.195
0.39
3.18
-
4.95
4
-
PLANE
SEATING
PLANE
-C-
A2
L
A
CL
B
B1
0.014
0.030
0.022
0.070
0.356
0.77
0.558
1.77
-
8
D1
B1
B
D1
e
0.010 (0.25) M
A1
e C
C A B S
e A
C
e B
C
D
D1
E
0.008
1.380
0.005
0.600
0.015
1.565
-
0.625
0.204
35.1
0.13
15.24
0.381
39.7
-
15.87
-
5
5
6
NOTES:
E1
0.485
0.580
12.32
14.73
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
e
e A
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS - 3.
e B
L
N
-
0.115
28
0.700
0.200
-
2.93
28
17.78
5.08
7
4
9
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Rev. 1 12/00
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and e A are measured with the leads constrained to be perpendic-
ular to datum -C- .
7. e B and e C are measured at the lead tips with the leads unconstrained.
e C must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
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