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参数资料
| 型号： | ICS1524AMT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 250 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封装： | 0.300INCH, SOIC-24 |
| 文件页数： | 6/24页 |
| 文件大小： | 354K |
| 代理商： | ICS1524AMT |
ICS1524A
14
ICS1524A Rev D 12/23/2005
I
2C Data Format
RANDOM REGISTER WRITE PROCEDURE
S 010011x W A
A
A P
7 bit address
register address
data
Acknowledge
STOP condition
START condition
WRITE command
Acknowledge
RANDOM REGISTER READ PROCEDURE
S 010011 X W A
A S 0 10011 X R A
A P
7 bit address
register address
7 bit address
data
Acknowledge
Repeat START
Acknowledge
STOP condition
START condition
WRITE command
Acknowledge
READ command
NO Acknowledge
SEQUENTIAL REGISTER WRITE PROCEDURE
S 010011 X W A
A
A P
7 bit address
register address
data
Acknowledge
Acknowledge Acknowledge
START condition
WRITE command
STOP condition
SEQUENTIAL REGISTER READ PROCEDURE
S 010011 X W A
A S 0 10011 X R A
A
A P
7 bit address
register address
7 bit address
data
Acknowledge
Repeat START
Acknowledge
NO Acknowledge
START condition
WRITE command
Acknowledge
READ command
Acknowledge STOP condition
Direction:
From bus host to device
From device to bus host
Note:
1.
All values are transmitted with the most-significant bit first and the least-significant bit last.
2.
The value of the X bit equals the logic state of pin 13 (I
2CADR).
3.
R = READ = 1 and W = WRITE = 0
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