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参数资料
| 型号： | ICS1567M-XXX-LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 180 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封装： | 0.300 INCH, SOIC-16 |
| 文件页数： | 5/11页 |
| 文件大小： | 161K |
| 代理商： | ICS1567M-XXX-LF |
Typical Output Configuration
Pin Description
PIN NUMBER
PIN SYMBOL
TYPE
DESCRIPTION
1
FS0
IN
Frequency Select LSB.
2
XTAL1
IN
Crystal Interface/External Oscillator Input.
3
XTAL2
OUT
Crystal Interface.
4
STROBE
IN
Control For Frequency Select Latch, also performs automatic
RAMDAC reset.
5
VSS
--
Device Ground (Both pins must be connected.)
6
VSS
--
Device Ground (Both pins must be connected.)
7
LD
OUT
Load Output. This output is at CLK frequency divided by N1.
8
FS4
IN
Frequency Select MSB.
9
CLK
OUT
Clock Output Inverted.
10
CLK
OUT
Clock Output Non-Inverted.
11
VDDO
--
Output Stage Power (Both pins must be connected).
12
VDDO
--
Output Stage Power (Both pins must be connected).
13
VDD
--
PLL System Power.
14
FS3
IN
Frequency Select.
15
FS2
IN
Frequency Select.
16
FS1
IN
Frequency Select.
= inputs with internal pull-up resistor
Notes:
CLK & CLK outputs are pseudo-ECL. Logic low level is set by the ratio of the resistors stacked across the power supply
VLO = (V supply
160)/(110 +160) in the example shown above.
The above values are a good starting point for RAMDAC or clock generator interface.
Figure 3
ICS1567
3
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