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参数资料
| 型号： | ICS1894K-32LFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 21/50页 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 32QFN |
| 标准包装： | 1 |
| 系列： | PHYceiver™ |
| 类型： | PHY 收发器 |
| 规程： | MII，RMII |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-VFQFPN 裸露焊盘（4x4） |
| 包装： | 标准包装 |
| 其它名称： | 800-2029-6 |
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
28
ICS1894-32
REV M 021512
Note 1:
Ignored if Auto negotiation is enabled.
Note 2:
CW = Command Override Write
LH = Latching High
LL = Latching Low
LMX = Latching Maximum
RO = Read Only
RW = Read/Write
RW/0 = Read/Write Zero
RW/1 = Read/Write One
SC = Self-clearing
SF = Special Functions
Note 3:
L = Latched on power-up/hardware reset
Whenever the PHY address is equal to 00000 (binary), the Isolate bit 0.10 is logic one, whenever the PHY address Is not equal to 00000, the
Isolate bit 0.10 is logic zero.
As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits.
Register
25 - Extended Control Register
25.15:12
Reserved
RW
0
25.11
Reserved
RW
0
6
25.10
Reserved
RW
1
25.9
TX10BIAS_SET
The normal output current of the Bias block for
10BaseT is 540uA. Changing the register can modify
the current with a step size of 5%
000: output 80% current
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
RW
1
25.8
0
25.7
04
25.6
TX100BIAS_SET
The normal output current of the Bias block for
100BaseTX is 180uA. Changing the register can
modify the current with a step size of 5%
000: output 80% current
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
RW
1
25.5
0
25.4
0
25.3
OUTDLY_CTL
This register controls the delay time of the digital
control signal for xmit_dac.
00: Longest delay time (same as original design)
01: Long delay time
10: Short delay time
11: Shortest delay time
RW
0
1
25.2
25.1
Reserved
RW
0
25.0
1
Register
26 - 31 - Extended Control Register (Reserved)
Bit
Definition
When Bit = 0
When Bit = 1
Access 2
SF2
Default3
Hex
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1894K-33LF | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894K-33LFT | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894K-34LF | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894K-34LFT | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894K-40LF | 功能描述:PHYCEIVER LOW PWR 3.3V 40QFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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