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参数资料
| 型号： | ICS2008BVLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/22页 |
| 文件大小： | 0K |
| 描述： | IC TIME CODE RCVR/GEN 44-PLCC |
| 标准包装： | 500 |
| 类型： | SMPTE 时间代码接收器，发生器 |
| 应用： | 多媒体 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
| 其它名称： | 2008BVLFT |
17
ICS2008B
ICS2008B
Reading VITC
To read VITC code one must first setup IR30 thru IR33. The
VITC Read Line registers, IR30 and IR31, select the video
line from which VITC code is to be read. The MSB is the en-
able for VITC reading. The Read Line field, bits 4 to 0, should
be programmed with the desired line number minus ten. So, if
line 15 is desired, a 5 should be programmed in the Read Line
field. If the read line field is set to 1Fh, this puts the VITC re-
ceiver into a scan mode. In scan mode, the VITC receiver
looks for a valid time code starting at line 10 for VITC1 or
VITC Read Line 1 for VITC2. The scan terminates when a
valid time code is received or the line count reads line 41.
IR32 selects the source and type of video. The GENLOCK
ENABLE bit must be set to a one, and the VTRES bit must be
set to a zero. The Video Interrupt Line register, IR33 should
be set to a line after all VITC read and write lines. This allows
all of the VITC receive and generate operations to be com-
plete before processing VITC.
The VLOCK bit in the SMPTE1 register indicates whether
the ICS2008B is genlocked to the selected video source.
Without the VLOCK status set to one, no VITC read will
occur.
When VLOCK is set to one and the control registers are prop-
erly initialized, VITC data are received a byte at a time from
the video signal and written to the VITC Read registers. At the
end of the VITC data frame the CRC byte is checked, and the
result reported in bit 5 of IR30 and IR31. In addition to the
CRC check, if a full VITC data frame is not received, the
NOCODE bit, bit 6, is set to a one.
Generating VITC
Like reading VITC, IR2E, IR2F, IR32 and IR33 must be setup
in order to generate VITC. The VITC Write Line registers,
IR2E and IR2F, select the video line to which VITC code is to
be written. The MSB is the enable for VITC generation. The
Write Line field, bits 4 to 0, should be programmed with the
desired line number minus ten. So, if line 12 is desired, a 2
should be programmed in the Write Line field. IR32 selects
the source and type of video. The GENLOCK ENABLE bit
must be set to a one, and the VTRES bit must be set to a zero.
The Video Interrupt Line register, IR33 should be set to a line
after all VITC read and write lines. This allows all of the
VITC receive and generate operations to be complete before
processing VITC.
With the VITC generator setup properly, when the selected
video line starts, the VITC data in the VITC Write buffer,
IR20 to IR27, is output. The video line interrupt, VLI in
SMPTE0, is provided to allow ample processing time for
VITC generation.
Burn-in Window
The burn-in window can be placed anywhere on the video
display. The position of the upper left corner of the window is
selected by the values written in IR28 and IR29. IR28 con-
trols the horizontal position. Values from 00h to 71h put the
corner in the first half of a video line (starting from the falling
edge of HSYNC). Values from 80h to F1h put the corner in
the second half of a video line. Any other values will not dis-
play the window. Care should be taken not to choose values
which put the window in any part of the blanking area. IR29
controls the vertical position. The value written here is the
video line number divided by 2.
IR3E controls the burn-in window character attributes. It con-
trols the size, normal and large, and the color of the characters
and background.
IR2A to IR2D, are the registers which control the characters
displayed in the burn-in window.
UART
The UART is accessed via two directly addressable registers,
the command/status register and the data register. On reset,
the UART is not operational. The command register must be
initialized before the UART will function.
Band rates are controlled in UART0 bits 1 and 0. 31.25 kHz
supports MIDI communications. 9600 Hz and 38.4 kHz sup-
port most serial VTR transport controls.
The UART has a four deep FIFO for its receive buffer. This
allows for relaxed interrupt latency requirements. In the case
of MIDI bit rates, the receiver will not overflow even if the
interrupt response delay is 1msec.
The UART’s transmitter has a buffer in front of the output
shift register so that a byte can be loaded and waiting for the
output shifter to be empty.
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