参数资料
型号: ICS2309MI-1LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 2309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 0.150 INCH, GREEN, SOIC-16
文件页数: 3/10页
文件大小: 238K
代理商: ICS2309MI-1LF
ICS2309
3.3 VOLT ZERO DELAY LOW SKEW BUFFER
ZERO DELAY BUFFERS
IDT / ICS 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
2
ICS2309
REV F 041906
Pin Assignment
Output Clock Mode Select Table
Note 1. Outputs are in high impedance state
Note 2. Buffer mode only; not zero delay between input and output
Pin Descriptions
12
1
11
2
10
CLKIN
CLKOUT
3
9
CLKA1
4
CLKA2
CLKA4
5
VDD
6
CLKA3
7
GND
8
CLKB1
VDD
GND
CLKB4
CLKB2
CLKB3
S2
S1
16
15
14
13
16 pin narrow (150 mil) SOIC
S2
S1
CLKA1:A4
CLKB1:B4
A & B Source
CLKOUT
PLL Status
0
Tri-state (note 1)
PLL
Driven
OFF
0
1
Running
Tri-state (note 1)
PLL
Driven
ON
1
0
Running
CLKIN (note 2)
PLL Bypass Mode
OFF
1
Running
PLL
Driven
ON
Pin
Number
Pin
Name
Pin Type
Pin Description
1
CLKIN
Input
Clock input (5 V tolerant).
2 - 3
CLKA1:A4
Output
Clock outputs A1:A4. See table above.
4
VDD
Power
Power supply. Connect to 3.3 V.
5
GND
Power
Connect to ground.
6 - 7
CLKB1:B4
Output
Clock outputs B1:B4. See table above.
8
S2
Input
Select input 2. See table above. Internal pull-up.
9
S1
Input
Select input 1. See table above. Internal pull-up.
10 - 11
CLKB1:B4
Output
Clock outputs B1:B4. See table above.
12
GND
Power
Connect to ground.
13
VDD
Power
Power supply. Connect to 3.3 V.
14 - 15
CLKA1:A4
Output
Clock outputs A1:A4. See table above.
16
CLKOUT
Input
Buffered output. Internal feedback on this pin.
相关PDF资料
PDF描述
ICS2309M-1LFT 2309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS2309M-1 2309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS2309MI-1 2309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS2309MI-1HLFT 2309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS2439-001F 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
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