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参数资料
| 型号： | ICS2494AN-XXX |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 135 MHz, VIDEO CLOCK GENERATOR, PDIP20 |
| 封装： | PLASTIC, DIP-20 |
| 文件页数： | 3/7页 |
| 文件大小： | 426K |
| 代理商： | ICS2494AN-XXX |
Applications
Layout Considerations
Utilizing the ICS2494/94A in video graphics adapter cards or
on PS2 motherboards is simple but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised in ensuring that components
not related to the ICS2494/94A do not share its ground. In
applications utilizing a multi-layer board, VSS should be di-
rectly connected to the ground plane. Multiple pins are utilized
for all analog and digital VSS and VDD connections to permit
extended frequency VCLK operation to 135 MHz. However,
in all cases, all VSS and VDD pins should be connected.
ICS2494A
Figure 2
Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between XTAL1 (1) and XTAL2 (2). In
IBM-compatible applications this will typically be a 14.31818
MHz crystal, but fundamental mode crystals between 10 MHz
and 25 MHz have been tested. Maintain short lead lengths
between the crystal and the ICS2494/94A. In some applica-
tions, it may be desirable to utilize the bus clock. If the signal
amplitude is equal to or greater than 3.5 volts, it may be
connected directly to XTAL1 (1). If the signal amplitude is less
than 3.5 volts, connect the clock through a .047 microfarad
capacitor to XTAL1 (1), and keep the lead length of the
capacitor to XTAL1 (1) to a minimum to reduce noise suscep-
tibility. This input is internally biased at VDD/2. Since TTL
compatible clocks typically exhibit a VOH of 3.5V, capaci-
tively coupling the input restores noise immunity.
The ICS2494/94A is not sensitive to the duty cycle of the bus
clock; however, the quality of this signal varies considerably
with different motherboard designs. As the quality of this
signal is typically outside of the control of the graphics adapter
card manufacturer, it is suggested that this signal be buffered
on the graphics adapter board. XTAL2 (2) must be left open in
this configuration.
Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2494/94A provide the bus clock for the rest of the system.
This eliminates the need for an additional 14.31818 MHz
crystal oscillator in the system, saving money as well as board
space. To do this, the XTALOUT (18) output should be buff-
ered with a CMOS driver.
Output Circuit Considerations
As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EMI.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK (19) or MCLK (12) and other
components in the system should be kept as short as possible.
The ICS2494/94A outputs have been designed to minimize
overshoot. In addition it may be helpful to place a ferrite bead
in these signal paths to limit the propagation of high order
harmonics of this signal. A suitable device would be a Ferrox-
cube 56-590-65/4B or equivalent. This device should be placed
physically close to the ICS2494/94A. A 33 to 47 Ohm series
resistor, sometimes called source termination, in this path may
be necessary to reduce ringing and reflection of the signal and
may reduce phase-jitter as well as EMI.
Digital Inputs
FS0 (4), FS1 (5), FS2 (7), and FS3 (8) are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired. STROBE (6), when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 3. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all zeros input state. MS0 (9), MS1 (11) and MS2 (3) are the
corresponding memory select inputs and are not strobed.
ICS2494
ICS2494A
3
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