参数资料
型号: ICS2509DGLF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封装: 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24
文件页数: 2/9页
文件大小: 149K
代理商: ICS2509DGLF
2
ICS2509C
0008D—03/31/03
Pin Descriptions
Note:
1.
Weak pull-ups on these inputs
PIN NUM BER
PIN NAM E
TYPE
DESCR IPTION
1
AGND
PWR
Analog Ground
2, 10, 15
VCC
PWR
Power Supply (3.3V)
3
CLKA0
OUT
Buffered clock output, Bank A
4
CLKA1
OUT
Buffered clock output, Bank A
5
CLKA2
OUT
Buffered clock output, Bank A
6, 7, 18, 19
GND
PWR
Ground
8
CLKA3
OUT
Buffered clock output, Bank A
9
CLKA4
OUT
Buffered clock output, Bank A
11
OEA
1
IN
Output enable (has internal pull_up). When high, normal operation.
When low bank A clock outputs are disabled to a logic low state.
12
FBOUT
OUT
Feedback output
13
FBIN
IN
Feedback input
14
OEB
1
IN
Output enable (has internal pull_up). When high, normal operation.
When low bank B clock outputs are disabled to a logic low state.
16
CLKB3
OUT
Buffered clock output. Bank B
17
CLKB2
OUT
Buffered clock output. Bank B
20
CLKB1
OUT
Buffered clock output. Bank B
21
CLKB0
OUT
Buffered clock output. Bank B
22
VCC
PWR
Power Supply (3.3V) digital supply.
23
AVC C
IN
Analog power supp ly (3.3V). When input is ground PLL is off and
bypassed.
24
CLKIN
IN
Clock input
Functionality
OEA
OEB
AVCC
CLKA
(0:4 )
CLKB
(0:3)
FBOUT
Source
0
3.33
0
Driven
PLL
N
0
1
3.33
0
Driven
PLL
N
1
0
3.33
Driven
0
Driven
PLL
N
1
3.33
Driven
PLL
N
00000
Driven
CLKIN
Y
0100
Driven
CLKIN
Y
1
0
Driven
0
Driven
CLKIN
Y
110
Driven
CLKIN
Y
Test mode:
When AVC C is 0, shuts off the PLL and connects the input directly to the output buffers
Buffer M ode
INPUTS
OUTPUTS
PLL
Shutdown
相关PDF资料
PDF描述
ICS2509GLF 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
ICS252PMI 200 MHz, OTHER CLOCK GENERATOR, PDSO8
ICS2694M-XXX-LF 135 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
ICS2694M-004 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
ICS2694M-004LF 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
相关代理商/技术参数
参数描述
ICS251 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
ICS2510C 制造商:ICS 制造商全称:ICS 功能描述:3.3V Phase-Lock Loop Clock Driver
ICS2510CG 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS,LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP(7x7) 包装:带卷 (TR)
ICS2510CGLF 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS,LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP(7x7) 包装:带卷 (TR)
ICS2510CGLFT 功能描述:IC CLOCK DVR PLL 3.3V 24-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS,LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP(7x7) 包装:带卷 (TR)