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参数资料
| 型号： | ICS251PMLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件页数： | 3/10页 |
| 文件大小： | 216K |
| 代理商： | ICS251PMLFT |
ICS251
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
IDT / ICS FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 2
ICS251
REV B 061306
Pin Assignment
8-pin (150 mil) SOIC
Output Clock Selection Table
Pin Descriptions
External Components
The ICS251 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a commonly
used trace impedance), place a 33
resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS251
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
X1 / I C L K
VD D
G N D
S0
S1
CL K
X2
1
2
3
4
8
7
6
5
PD T S
S1
S0
CLK (MHz)
Spread
Percentage
0
User
Configurable
User
Configurable
01
User
Configurable
User
Configurable
10
User
Configurable
User
Configurable
11
User
Configurable
User
Configurable
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
S0
Input
Select pin 0 for frequency selection on CLK. Internal pull-up resistor.
2
VDD
Power
Connect to +3.3 V.
3
X1/ICLK
XI
Connect this pin to a crystal or external clock input.
4
X2
XO
Connect this pin to a crystal, or float for clock input.
5
CLK
Output
Clock output. Weak internal pull-down when tri-state.
6
S1
Input
Select pin 1 for frequency selection on CLK. Internal pull-up resistor.
7
GND
Power
Connect this to Ground.
8PDTS
Input
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up
resistor.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS251PMT | 功能描述:IC CLK SYNTHESIZER FP SGL 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:VersaClock™ 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS252 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER |
| ICS252MI-52LF | 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER PLL 8SOIC 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER FP DUAL 8SOIC |
| ICS252MI-52LFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER PLL 8SOIC 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER FP DUAL 8SOIC |
| ICS252MIP | 制造商:ICS 制造商全称:ICS 功能描述:Field Programmable Dual Output SS VersaClock Synthesizer |
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