参数资料
型号: ICS252PMT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 1/11页
文件大小: 221K
代理商: ICS252PMT
DATASHEET
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
ICS252
IDT / ICS FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1
ICS252
REV C 061306
Description
The ICS252 is a low cost, dual-output, field programmable
clock synthesizer. The ICS252 can generate two output
frequencies from 314 kHz to 200 MHz using up to two
independently configurable PLLs. The outputs may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
Using ICS’ VersaClocksoftware to configure the PLL and
output, the ICS252 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include 4 selectable configuration registers.
The device employs Phase-Locked Loop (PLL) techniques
to run from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
The device also has a power-down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS252 is also available in factory programmed custom
versions for high-volume applications.
Features
8-pin SOIC package
Two addressable registers
Input crystal frequency of 5 to 27 MHz
Clock input frequency of 3 to 150 MHz
Output clock frequencies up to 200 MHz
Configurable Spread Spectrum Modulation
Operating voltage of 3.3 V
Replaces multiple crystals and oscillators
Controllable output drive levels
Advanced, low-power CMOS process
Available in RoHS 5 (green) or RoHS 6 (green and lead
free) compliant package
Block Diagram
Crystal
Oscillator
GND
VDD
PDTS
PLL2
Divide
Logic
and
Output
Enable
Control
SEL
CLK2
CLK1
OTP
ROM
with
PLL
Values
X2
Crystal
External capacitors
are required.
X1
PLL1
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