参数资料
型号: ICS309RLFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/10页
文件大小: 0K
描述: IC SRL PROGR TRPL PLL CLK 20QSOP
标准包装: 2,500
系列: VersaClock™
类型: 时钟/频率合成器
PLL: 带旁路
输入: 时钟,晶体
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 1:9
差分 - 输入:输出: 无/无
频率 - 最大: 200MHz
除法器/乘法器: 无/是
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
供应商设备封装: 20-QSOP
包装: 带卷 (TR)
其它名称: 309RLFT
DATASHEET
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH
ICS309
IDT SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH
1
ICS309
REV L 091311
Description
The ICS309 is a versatile serially-programmable, triple
PLL with spread spectrum clock source. The ICS309
can generate any frequency from 250kHz to 200 MHz,
and up to 6 different output frequencies simultaneously.
The outputs can be reprogrammed on-the-fly, and will
lock to a new frequency in 10 ms or less.
To reduce system EMI emissions, spread spectrum is
available that supports modulation frequencies of
31 kHz and 120 kHz, as well as modulation amplitudes
of +/-0.25% to +/-2.0%. Both center and down-spread
options are available.
The device includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS309 default for non-programmed start-up are
buffered reference clock outputs on all clock output
pins.
IDT’s VersaClockTM programming software allows the
user to configure up to 9 outputs with target
frequencies, spread spectrum capabilities or buffered
reference clock outputs. The VersaClockTM software
automatically configures the PLLs for optimal overall
performance.
Features
Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS
compliant
Highly accurate frequency generation
M/N Multiplier PLL: M = 1..2048, N = 1..1024
Serially programmable: user determines the output
frequency via a 3-wire interface
Spread Spectrum frequency modulation for reduced
system EMI
Center or Down Spread up to 4% total
Selectable 32 kHz and 120 kHz modulation
Eliminates need for custom quartz oscillators
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 3 - 50 MHz
Output clock frequencies up to 200 MHz
Operating voltage of 3.3 V
Up to 9 reference clock outputs
Power down tri-state mode
Very low jitter
Block Diagram
C rystal
O sc illator
PLL1 with
Spread
Spectrum
GND
2
3
VDD
PD T S
PLL2
PLL3
Divide
Logic
and
Output
Enable
Control
CLK1
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
X2
C rystal or
clock input
E xternal capacitors are
required w ith a crystal input.
X 1/IC LK
SCLK
DATA
STROBE
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参数描述
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