参数资料
型号: ICS650R-27ILFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/7页
文件大小: 0K
描述: IC CLOCK SYNTHESIZER 20-SSOP
标准包装: 1
类型: 时钟/频率合成器
PLL:
输入: 时钟,晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:7
差分 - 输入:输出: 无/无
频率 - 最大: 133.33MHz
除法器/乘法器: 是/无
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
供应商设备封装: 20-QSOP
包装: 标准包装
其它名称: 800-1813-6
DATASHEET
NETWORKING CLOCK SOURCE
ICS650-27
IDT / ICS NETWORKING CLOCK SOURCE
1
ICS650-27
REV F 051310
Description
The ICS650-27 is a low cost, low jitter, high performance
clock synthesizer for networking applications. Using analog
Phase-Locked Loop (PLL) techniques, the device accepts a
12.5 MHz or 25 MHz clock or fundamental mode crystal
input to produce multiple output clocks for networking chips,
PCI devices, SDRAM, and ASICs. The ICS650-27 outputs
all have zero ppm synthesis error.
The ICS650-27 is pin compatible and functionally
equivalent to the ICS650-07. It is a performance
upgrade and is recommended for all new 3.3V designs.
See the MK74CB214, ICS551, and ICS552-01 for non-PLL
buffer devices which produce multiple low-skew copies of
these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay buffers
that can synchronize outputs and other needed clocks.
Features
Packaged in 20-pin (150 mil) SSOP (QSOP)
Pb (lead) free package, RoHS compliant
12.5 MHz or 25 MHz fundamental crystal or clock input
Six output clocks with selectable frequencies
SDRAM frequencies of 67, 83, 100, and 133 MHz
Buffered crystal reference output
Zero ppm synthesis error in all clocks
Ideal for PMC-Sierra’s ATM switch chips
Full CMOS output swing with 25 mA output drive
capability at TTL levels
Advanced, low-power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature only
Block Diagram
Clock
Buffer/
Crystal
Oscillator
Clock
Synthesis
and Control
Circuitry
25 or 12.5 MHz
cyrstal or clock
ACS1:0
CLKA1
CCS
GND
2
BCS1:0
2
X1/ICLK
X2
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
REFOUT
VDD
2
/2
OE (all outputs)
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