参数资料
型号: ICS354G-XXT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO16
封装: TSSOP-16
文件页数: 3/5页
文件大小: 71K
代理商: ICS354G-XXT
MDS 354 B
3
Revision 021202
Integrated Circuit Systems, Inc. 525 Race Street San Jose, CA, 95126 (408) 295-9800tel www.icst.com
ICS354
Triple PLL Quick Turn Clock Synthesizer
External Components / Crystal Selection
The ICS354 requires a 0.01F decoupling capacitor to be connected between VDD and GND on pins 5 and 6, and
another between pins 12 and 11. These must be connected close to the ICS354 to minimize lead inductance. No
external power supply filtering is required for this device. A 33
series terminating resistor can be used next to
each CLK pin. For a crystal input, a parallel resonant, fundamental mode crystal should be used. Crystal capacitors
must be connected from each of the pins X1 and X2 to Ground. The value (in pF) of these crystal caps should equal
(CL-6pf)*2, where CL is the crystal load capacitance in pF. As an example, for a crystal with 16 pF load capacitance,
each crystal capacitor would be 20 pF [(16 - 6pf)*2 = 20].
For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either X1 or X2).
Frequency Select Table
The ICS354 can be configured so that one PLL provides up to 4 frequency selections. For example, CPU
frequencies of 66.7 MHz, 100.0 MHz, 133.3 MHz, and 166.7 MHz could be included. This information should be
indicated on the Order Form when the ICS354 is initially defined.
Device Configuration
The ICS354 QTClock provides the facility for up to 5 clock outputs. The outputs are derived from either the
reference input or from one of the 3 PLLs. All chip functions are controlled from an OTP ROM which has 3 input
control lines (S2, S1, S0), giving a total of 8 address locations. Each address location gives control of the following:
1) Each output can be turned off individually.
2) The internal dividers for each PLL are controlled to generate any required frequency.
3) Each PLL can be turned off (powered down) individually.
4) The spread spectrum function available on PLLA can be enabled or disabled.
5) The output divide and control logic can be configured to bring the appropriate clock to the correct pin.
6) Up to two low skew copies of the same clock can be enabled.
This chip architecture provides the user with unrivaled flexibility. For example, one of the input pins could be
dedicated to enabling/disabling spread spectrum, a second could be used to control the power of the chip by
shutting down PLLs and outputs when not used. The third could be used to change the output clock frequencies.
The specification is complete when the ICS354 QTClock Order Form accompanies this data sheet. The order form
lists the input and CLK actual frequencies, as well as any other available options. This unique configuration is given
a two character alphanumeric programming code (ICS354-xx), which must be specified when referring to samples.
相关PDF资料
PDF描述
ICS355R-XX 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS355R-XX-LF 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS355R-XXI 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS355R-XXT-LF 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS355R-XXT 200 MHz, OTHER CLOCK GENERATOR, PDSO20
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