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参数资料
| 型号： | ICS504MT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.7 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| 封装： | SOIC-8 |
| 文件页数： | 3/4页 |
| 文件大小： | 53K |
| 代理商： | ICS504MT |
ICS504
Intel i740 Graphics Clock Source
MDS504A
3
Revision 6018
Printed 6/1/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY
PRELIMINARY INFORMATION
INFORMATION
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Output
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3 V unless otherwise noted)
Operating Voltage, VDD
3
5.5
V
Input High Voltage, VIH, ICLK only
ICLK (Pin 1)
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, ICLK only
ICLK (Pin 1)
VDD/2
(VDD/2)-1
V
Input High Voltage, VIH
Pins 6 and 7
2
V
Input Low Voltage, VIL
Pins 6 and 7
0.8
V
Input High Voltage, VOH
IOH = -4 mA
VDD-0.5
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
IDD Operating Supply Current
No load
15
mA
Short Circuit Current
CLK output
±40
mA
On-Chip Pull-up Resistor, SEL and OE
Pins 6 and 7
270
k
Input Capacitance, SEL and OE
Pins 6 and 7
4
pF
AC CHARACTERISTICS (VDD = 3.3 V unless otherwise noted)
Input Frequency, crystal input
13.5
MHz
Input Frequency, clock input
13.5
MHz
Actual mean frequency error vs target
48.0, 66.667 MHz
0
ppm
Output Clock Rise Time
0.8 to 2.0V
1
ns
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle
at VDD/2
40
60
%
Absolute Clock Period Jitter
Deviation from mean
±120
ps
One Sigma Clock Period Jitter
50
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Typical values are at 25°C.
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