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参数资料
| 型号： | ICS525RI-12LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 62.5 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, MO-153, SSOP-28 |
| 文件页数： | 8/10页 |
| 文件大小： | 232K |
| 代理商： | ICS525RI-12LF |
ICS525-01/02/11/12
USER CONFIGURABLE CLOCK
CLOCK MULTIPLIER
IDT / ICS USER CONFIGURABLE CLOCK
7
ICS525-01/02/11/12 REV S 042407
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Short Circuit Current
CLK and REF outputs
±55
mA
Input Capacitance
CIN
V, R, S pins and pin 19
4
pF
On-chip Pull-up Resistor
RPU
V, R, S pins and pin 19
270
k
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
FIN
Crystal input
5
27
MHz
Clock input
2
50
MHz
Output Clock Rise Time
0.8 to 2.0 V
1
ns
Output Clock Fall Time
2.0 to 0.8 V
1
ns
Output Clock Duty Cycle, OD =
2, 4, 6, 8, or 10
At VDD/2
45
49 to
51
55
%
Output Clock Duty Cycle, OD =
3, 5, 7, or 9
At VDD/2
40
60
%
Output Clock Duty Cycle, OD =
1 (-02 and -12 only)
At VDD/2
35
65
Power-down Time, PD low to
clocks stopped
50
ns
Power-up Time, PD high to
clocks stable
10
ms
Absolute Clock Period Jitter,
ICS525-01, Note 2
tja
Deviation from mean
±140
ps
One Sigma Clock Period Jitter,
ICS525-01, Note 2
tjs
One Sigma
45
ps
Absolute Clock Period Jitter,
ICS525-02, Note 2
tja
Deviation from mean
±85
ps
One Sigma Clock Period Jitter,
ICS525-02, Note 2
tjs
One Sigma
30
ps
Absolute Clock Period Jitter,
ICS525-11, Note 2
tja
Deviation from mean
±160
ps
One Sigma Clock Period Jitter,
ICS525-11, Note 2
tjs
One Sigma
40
ps
Absolute Clock Period Jitter,
ICS525-12, Note 2
tja
Deviation from mean
±160
ps
One Sigma Clock Period Jitter,
ICS525-12, Note 2
tjs
One Sigma
40
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS525RI12LFT | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Clock |
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| ICS527-03 | 制造商:ICS 制造商全称:ICS 功能描述:Clock Slicer User Configurable PECL Output Zero Delay Buffer |
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