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参数资料
| 型号： | ICS525RI12LFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 50 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, LEAD FREE, MO-153, SSOP-28 |
| 文件页数： | 5/9页 |
| 文件大小： | 178K |
| 代理商： | ICS525RI12LFT |
User Configurable Clock
MDS 525-01/02/11/12 R
5
Revision 042506
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-01/02/11/12 requries two 0.01F
decoupling capacitors to be connected between VDD
and GND, one on each side of the chip. The capacitor
must be connected close to the device to minimize lead
inductance.
External Resistors
A 33
series termination resistor should be used on
the CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the tables on pages
3-4. To replace a standard oscillator, users should
connect the divider select input pins directly to ground
(or VDD, although this is not required because of
internal pull-ups) during Printed Circuit Board layout.
The ICS525 will automatically produce the correct
frequency when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
Configuration Pin Settings
The output of the ICS525 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127 (0 not
permitted for ICS525-01/-11)
VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not
permitted for ICS525-01/-11)
Output Divider (OD) = values on pages 3-4
Also, the following operating ranges should be
observed:
1. The output frequency must be in the ranges listed on
pages 3-4.
2. The phase detector frequency must be above 200
kHz.
Since all of the inputs have pull-up resistors, it is only
necessary to ground the pins that need to be set to
zero.
Which Part to Use?
The ICS525-01 is the original configurable clock.
The ICS525-02 has a higher maximum output
grequency and a slightly different set of output dividers.
The ICS525-11 has the same divider set as the -01 but
is optimized for low frequency operation.
The ICS525-12 has the same divider set as the -02 but
is optimized for low frequency operation.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site.
CLK Frequency
Input Frequency 2x
VDW 8
+
()
RDW 2
+
() OD
---------------------------------------------
×
=
200kHz InputFrequency
RDW 2
+
()
-----------------------------------------------
<
相关PDF资料 |
PDF描述 |
|---|---|
| ICS525-01RLF | 160 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-02LF | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS527R-01IT | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-01LFT | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-01LFT | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS525RI-12T | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Clock |
| ICS527-01 | 制造商:ICS 制造商全称:ICS 功能描述:Clock Slicer⑩ User Configurable Zero Delay Buffer |
| ICS527-02 | 制造商:ICS 制造商全称:ICS 功能描述:Clock Slicer User Configurable PECL Input Zero Delay Buffer |
| ICS527-03 | 制造商:ICS 制造商全称:ICS 功能描述:Clock Slicer User Configurable PECL Output Zero Delay Buffer |
| ICS527-04 | 制造商:ICS 制造商全称:ICS 功能描述:Clock Slicer User Configurable PECL input Zero Delay Buffer |
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