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| 型号： | ICS527R-02 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.150 INCH, 0.635 MM PITCH, MO-153, SSOP-28 |
| 文件页数： | 2/9页 |
| 文件大小： | 255K |
| 代理商： | ICS527R-02 |
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
2
Revision 022806
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-02
Pin Assignment
28-pin 150 mil body SSOP
Output Frequency Range Table
CLK2 Operation Table
Pin Descriptions
18
7
17
8
16
9
15
PE C L IN
10
PE C L IN
11
GN D
12
CL K 2
13
OE C L K 2
14
F0
GN D
PDTS
FB IN
F1
F6
F4
F2
F5
22
21
20
19
F3
CL K 1
5
6
S1
VD D
VDD
24
23
R0
3
4
DIV 2
S0
R1
26
25
R2
1
2
R5
R6
R3
28
27
R4
S1 S0
Output Frequency (MHz)
Commercial
Industrial
0
10 - 50
16 - 45
0
1
5 - 40
8 - 33
1
0
4 - 10
4 - 8
1
20 -160
32 - 140
OECLK2
DIV2
CLK2
0X
Z
1
0
SYNC
11
CLK1/2
Pin
Number
Pin
Name
Pin
Type
Pin Description
1,2, 24-28
R5, R6,
R0-R4
Input
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
3
DIV2
Input
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
4, 5
S0, S1
Input
Select pins for output divider determined by user. See table above. Internal
pull-up.
6, 23
VDD
Power
Connect to +3.3 V.
7
PECLIN
Input
True PECL input clock.
8
PECLIN
Input
Complementary PECL input clock.
9, 20
GND
Power
Connect to ground
10
OECLK2
Input
CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up.
11-17
F0-F6
Input
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
18
FBIN
Input
Feedback clock input
19
PDTS
Input
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
21
CLK2
Output
Output clock 2. Can be SYNC pulse or a low skew divide by 2 of CLK1.
22
CLK1
Output
Output clock 1.
ICS527-02
Clock Slicer User Configurable PECL Input Zero Delay Buffer
TSD
IDT / ICS Clock Slicer User Configurable PECL Input Zero Delay Buffer
ICS527-02
2
相关PDF资料 |
PDF描述 |
|---|---|
| ICS527R-04LF | 527 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-04T | 527 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-04 | 527 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-04LFT | 527 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS527R-04 | 527 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS527R-02I | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS527R-02ILF | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP |
| ICS527R-02ILFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP |
| ICS527R-02IT | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS527R-02LF | 功能描述:IC CLK SLICER ZDB CONFIG 28-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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