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参数资料
| 型号： | ICS548G-06LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 2/5页 |
| 文件大小： | 93K |
| 代理商： | ICS548G-06LF |
LOCO PLL CLOCK MULTIPLIER
MDS 548-06 B
2
Revision 080103
In tegr at ed C i rcui t S ystems ● 525 Ra ce S t ree t, San Jose, C A 95126 ● tel (408) 295 -9800 ●
w w w. icst . com
ICS548-06
Pin Assignment
Reference Clock Output Table
Clock Output Table
Pin Descriptions
12
1
11
2
10
3
9
X1/ICLK
4
VDD
5
VDD
6
DC
7
REFSEL
8
GND
PDCLK2
OE
DC
GND
S0
CLK1
REF
CLK2
16
15
14
13
S1
X2
16-Pin 173 Mil (0.65mm) TSSOP
REFSEL
REF
0ON
1OFF
S1
S0
CLK1
CLK2
0
4X input
2X input
0
M
5.333X input
2.667X input
0
1
5X input
2.5X input
M
0
2.5X input
1.25X input
M
2X input
1X input
M
1
3.333X input
1.667X input
1
0
6X input
3X input
1
M
3X input
1.5X input
1
8X input
4X input
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/ICLK
Input
Crystal connection or clock input.
2
VDD
Power
Connect to +3.3V or +5.0V. Must be the same as pin 3.
3
VDD
Power
Connect to +3.3V or +5.0V. Must be the same as pin 2.
4
REFSEL
Input
Turns off reference clock when high. Internal pull-up.
5
GND
Power
Connect to ground.
6
GND
Power
Connect to ground.
7
REF
Output
Reference clock output.
8
S1
Input
Multiplier select pin 1. Connect to GND, VDD or float.
9
CLK1
Output
Clock1 output per table above.
10
CLK2
Output
Clock2 output per table above.
11
S0
Input
Multiplier select pin 0. Connect to GND, VDD or float.
12
DC
-
Do not connect anything to this pin.
13
OE
Input
Output enable.
14
PDCLK2
Input
Turns off Clock2 when high. Internal pull-up.
15
DC
-
Do not connect anything to this pin.
16
X2
Input
Crystal connection. Leave unconnected for clock input.
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