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参数资料
| 型号： | ICS548G-06LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 4/5页 |
| 文件大小： | 93K |
| 代理商： | ICS548G-06LF |
LOCO PLL CLOCK MULTIPLIER
MDS 548-06 B
4
Revision 080103
In tegr at ed C i rcui t S ystems ● 525 Ra ce S t ree t, San Jose, C A 95126 ● tel (408) 295 -9800 ●
w w w. icst . com
ICS548-06
DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature 0 to +70
°C, unless stated otherwise
Note: 1. Using a 20MHz crystal input, outputs of 100MHz and 50MHz.
AC Electrical Characteristics
VDD = 3.3V ±10%, Ambient Temperature 0 to +70
° C, unless stated otherwise
Note:1. The phase relationship between input and output clocks can change at power up. For a fixed phase
relationship, see the ICS570 or the ICS527.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
V
Input High Voltage, ICLK only
VIH
Pin 1
(VDD/2)+1
VDD/2
5.5
V
Input Low Voltage, ICLK only
VIL
Pin 1
VDD/2
(VDD/2)-1
V
Input High Voltage, S0, S1
VIH
VDD-0.5
V
Input Low Voltage, S0, S1
VIL
0.5
V
Output High Voltage
VOH
IOH = -8 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -25 mA
2.4
V
Output Low Voltage
VOL
IOL = 20 mA
0.4
V
Short Circuit Current
IOS
Each output
±70
mA
Operating Supply Current
IDD
Note 1
11
mA
Input Capacitacnce, S1, S0
CIN
5pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency, crystal input
5
27
MHz
Input Frequency, clock input
2
50
MHz
Output Frequency, VDD=5V
14
200
MHz
Output Frequency, VDD=3.3V
14
160
MHz
Output Rise Time
tOR
0.8 to 2.0 V, CL=15 pF
600
ps
Output Fall Time
tOF
2.0 to 0.8 V, CL=15 pF
600
ps
Output clock duty cycle
at VDD/2
45
49 to 51
55
%
Absolute Clock Period Jitter
Deviation from mean
±150
ps
One Sigma Clock Period Jitter
75
ps
Skew
CLK1 to CLK2
-250
250
ps
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