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参数资料
| 型号： | ICS552G-02LF |
| 元件分类： | 时钟及定时 |
| 英文描述： | 552 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 2/6页 |
| 文件大小： | 96K |
| 代理商： | ICS552G-02LF |
LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK
MDS 552-02 B
2
Revision 050401
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PRE L IMINA R Y INF O RMA T IO N
ICS552-02
Pin Assignment
Input Source Select
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01
F should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33
series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-02 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30
series termination
on one output (with 33
on the others) will cause at least 15ps of skew.
12
1
11
2
10
3
9
OE
4
VDD
5
Q0
6
VDD
7
Q1
8
Q2
Q7
Q6
Q5
Q3
Q4
INA
GND
16
15
14
13
INB
SELA
16 Pin TSSOP
SELA
Input
0INB
1INA
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
OE
Input
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
2
VDD
Power
Connect to +2.5V, +3.3V or +5.0V. Must be the same as pin 15.
3
Q0
Output
Clock Output 0
4
Q1
Output
Clock Output 1
5
Q2
Output
Clock Output 2
6
Q3
Output
Clock Output 3
7
GND
Power
Connect to ground.
8
INB
Input
Clock Input B. 5V tolerant input.
9
INA
Input
Clock Input A. 5V tolerant input.
10
GND
Power
Connect to ground.
11
Q4
Output
Clock Output 4
12
Q5
Output
Clock Output 5
13
Q6
Output
Clock Output 6
14
Q7
Output
Clock Output 7
15
VDD
Power
Connect to + 2.5V, +3.3V or +5.0V. Must be the same as pin 2.
16
SELA
Input
Selects either INA or INB. Internal pull-up resistor.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS552G-02LF | 552 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS552R-01B | 552 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS552R-01BILF | 552 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS552R-01BI | 552 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS552R-01B | 552 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS552G-02T | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER |
| ICS552G-03 | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) |
| ICS552G-03T | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) |
| ICS552R-01 | 功能描述:IC OSC/MULT/BUFFER OCT 20-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS552R-01I | 功能描述:IC OSC/MULT/BUFFER OCT 20-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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