参数资料
型号: ICS581G-01ILF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 581 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16
文件页数: 4/9页
文件大小: 167K
代理商: ICS581G-01ILF
Zero Delay Glitch-Free Clock Multiplexer
MDS 581-01/02 H
4
Revision 050206
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS581-01/02
Note that the clock driving the FBIN pin must not be
tri-stated unless the PLL is powered down. Otherwise
the PLL will run in an open loop.
The ICS581-02 is identical to the ICS581-01 except for
the switching of the input mux. On the ICS581-02, the
switching is automatically controlled by a transition
detector. The transition detector monitors the clock on
INA. If this clock stops, the output of the detector,
NO_INA goes high, which then selects clock input INB
to the mux. The definition of the clock stopping is
determined by a timeout selected by input DIV. If DIV is
low, NO_INA will go high after no transitions have
occurred on INA for nominally three cycles of the clock
on INB. If DIV is high, the timeout is nominally 48
cycles of INB. When INA restarts, the mux immediately
switches back to the INA selection with no timeout.
Input Clock Frequency
The ICS581-01 and ICS581-02 are designed to switch
between two clocks of the same frequency. They will
also operate with different frequencies on each of the
two input clocks. If the two input frequencies require
different input ranges (see table on page two), then the
highest range should be permanently selected. When
the selected input clock is outside this range, jitter and
input skew specifications may not be met. Consult ICS
for more information.
Application Example
A typical application for the ICS581-02 is to provide a backup clock for a system. The backup reliable clock
would be connected to INB while the main clock would be connected to INA. If the main clock failed, the
ICS581-02 would automatically be switched to the backup clock. The following example shows the
connection for this.
In this example, the clocks are 155 MHz and so the frequency range is address 11. Both S0 and S1 are left
unconnected, causing the on-chip pull-ups to produce the required high inputs. The same is true for OE0,
OE1, and DIV. In this example, CLK4 is used as the feedback. Note that the feedback path is before the
series resistor.
CLK3
S0
CLK4
S1
GND
VDD
OE1
INA
INB
GND
FBIN
OE0
DIV
VDD
CLK1
CLK2
VDD
0.01 F
33
0.01 F
MAIN
BACKUP
相关PDF资料
PDF描述
ICS581G-02I 581 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS601M-02IT 170 MHz, OTHER CLOCK GENERATOR, PDSO16
ICS650R-01ILF 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20
ICS650R-01LF 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20
ICS650R-01T 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20
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