参数资料
型号: ICS601R-25LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 156 MHz, OTHER CLOCK GENERATOR, PDSO20
封装: 0.150 INCH, ROHS COMPLIANT, SSOP-20
文件页数: 2/6页
文件大小: 212K
代理商: ICS601R-25LF
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
MDS 601-25 C
2
Revision 071505
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 297-1 201 www.icst.com
ICS601-25
Pin Assignment
Output Select Table
Pin Descriptions
5
GND
6
7
8
9
10
CLK3
GND
VDD
PD
S3
CLK1
VDD
S1
S2
CLK5
CLK4
16
15
14
13
12
11
20 Pin (150 mil) SSOP
3
4
VDD
CLK2
VDD
18
S0
17
1
2
VDD
GND
X2
20
X1/ICLK
19
S3
S2
S1
S0
Multiplier
00
0
x1
00
0
1
x2
00
1
0
x3
00
1
x4
01
0
x5
01
0
1
x6
01
1
0
x8
0
1
x16
10
0
x7
10
0
1
x9
1
0
1
0
x10
1
0
1
x11
1
0
x12
1
0
1
output tristates
1
0
x14
1
x15
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/ICLK
XI
Crystal or clock input. Connect to a 10-27 MHz fundamental parallel mode
crystal or clock input.
2
VDD
Power
Connect to +3.3 V.
3
S0
Input
Select pin 0. Internal pull-up.
4, 5
VDD
Power
Connect to +3.3 V.
6
S1
Input
Select pin 1. Internal pull-up.
7
GND
Power
Connect to ground.
8
S3
Input
Select pin 3. Internal pull-down.
9PD
Input
Powerdown when held low. Internal pull-up.
10
S2
Input
Select pin 2. Internal pull-up.
11
CLK1
Output
Clock output.
12
VDD
Power
Connect to +3.3 V.
13
CLK5
Output
Clock output.
14
CLK4
Output
Clock output.
15
GND
Power
Connect to ground.
16
CLK3
Output
Clock output.
17
CLK2
Output
Clock output.
18
VDD
Power
Connect to +3.3 V.
19
GND
Power
Connect to ground.
20
X2
XO
Crystal connection. Connect to a 10-27 MHz fundamental parallel mode
crystal or leave unconnected for clock input.
ICS601-25
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
TSD
IDT / ICS LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
ICS601-25
2
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