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| 型号： | ICS671M-03IT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 671 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 3/9页 |
| 文件大小： | 196K |
| 代理商： | ICS671M-03IT |
ICS671-03
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ZDB AND MULTIPLIER
IDT 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
3
ICS671-03
REV B 112706
External Components
The ICS671-03 requires a minimum number of external
components for proper operation. Decoupling capacitors of
0.01F should be connected between VDD and GND on
pins 4 and 5, and VDD and GND on pins 13 and 12, as close
to the device as possible. A series termination resistor of 33
may be used close to each clock output pin to reduce
reflections.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50
trace (a commonly used trace
impedance) place a 33
resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20
.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33
series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS671-03. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
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| ICS671M-06IT | 671 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS674R-01I | SPECIALTY LOGIC CIRCUIT, PDSO28 |
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| ICS680G-01T | 66.6666 MHz, OTHER CLOCK GENERATOR, PDSO24 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS671M-06I | 制造商:ICS 制造商全称:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILFT | 制造商:ICS 制造商全称:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06IT | 制造商:ICS 制造商全称:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS672-01 | 制造商:ICS 制造商全称:ICS 功能描述:QuadraClock⑩ Quadrature Delay Buffer |
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