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参数资料
| 型号： | ICS680G-01T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6666 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封装： | 0.173 INCH, TSSOP-24 |
| 文件页数： | 3/8页 |
| 文件大小： | 149K |
| 代理商： | ICS680G-01T |
Networking Clock Synthesizer and Zero Delay Buffer
MDS 680-01 F
3
Revision 020305
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS680-01
External Components
The ICS680-01 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD (pins 5 and 16) and GND (pins 6 and
15), as close to these pins as possible. For optimum
device performance, the decoupling capacitor should
be mounted on the component side of the PCB. Avoid
the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50
trace (a commonly
used trace impedance) place a 33
resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation crystal caps (pF) = (CL-6)x2
In the equation, CL is the crystal load capacitance. So
for a crystal with a 16 pF load capacitance, two 20
pF[(16-6)x2] capacitors should be used
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33
series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS680-01. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
18
VDD
Power
Connect to voltage supply.
19
ICLK
Input
Zero Delay Buffer Input. Weak Internal pull-up.
20
25M
Output
25 MHz reference output clock. Weak internal pull-down when tri-state.
21
S1
Input
Select pin 1. See table above.
22
PDTS
Power
Power-down tri-state. Powers down entire chip and tri-states outputs
when low. Internal pull-up resistor.
23
VDD
Power
Connect to voltage supply.
24
X2
XO
Crystal output. Connect this pin to a crystal. Float for clock input.
Pin
Number
Pin
Name
Pin
Type
Pin Description
相关PDF资料 |
PDF描述 |
|---|---|
| ICS7151M-40LF | 133.4 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS7151M-50 | 16.7 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS7151MI-20LF | 66.7 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS7151MI-50 | 16.7 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS7151MI-10 | 33.4 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS68-1 | 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum Orange |
| ICS69-1 | 制造商:Thomas & Betts 功能描述:SEALEEVE |
| ICS6953BI147 | 制造商:ICS 制造商全称:ICS 功能描述:DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER |
| ICS70-1 | 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum |
| ICS71-1 | 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum |
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