参数资料
型号: ICS810001DK-21LF
厂商: IDT, Integrated Device Technology Inc
文件页数: 3/19页
文件大小: 0K
描述: IC CLK GEN SYNC VCXO DL 32VFQFN
标准包装: 490
系列: HiPerClockS™, FemtoClock™
类型: 时钟/频率发生器,转换器,抖动衰减器,多路复用器
PLL:
主要目的: 视频
输入: LVCMOS,LVTTL
输出: LVCMOS,LVTTL
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 无/无
频率 - 最大: 175MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-VFQFPN 裸露焊盘(4x4)
包装: 托盘
其它名称: 800-2276
ICS810001DK-21LF-ND
ICS810001DK-21 REVISION B APRIL 13, 2010
11
2010 Integrated Device Technology, Inc.
ICS810001-21 Data Sheet
FEMTOCLOCK DUAL VCXO VIDEO PLL
Applications Information
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k
resistor can be used.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform ance,
power supply isolation is required. The ICS810001-21 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA, VDDO and VDDX should be
individually connected to the power supply plane through vias, and
0.01F bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10
resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
Figure 1. Power Supply Filtering
VDD
VDDX
VDDA
3.3V
10
10
10F
.01F
10F
.01F
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