参数资料
型号: ICS830154AMI-08LFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/16页
文件大小: 0K
描述: IC CLOCK BUFFER 1:4 160MHZ 8SOIC
标准包装: 2,500
系列: HiPerClockS™
类型: 扇出缓冲器(分配)
电路数: 1
比率 - 输入:输出: 1:4
差分 - 输入:输出: 无/无
输入: LVCMOS
输出: LVCMOS
频率 - 最大: 160MHz
电源电压: 1.4 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
ICS830154AGI-08 REVISION A MARCH 29, 2010
7
2010 Integrated Device Technology, Inc.
ICS830154I-08 Data Sheet
OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER
Table 5D. AC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to FOUT ≤ 150MHz.
NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
160
MHz
tpLH
Propagation Delay
(low to high transition); NOTE 1
1.5
2.7
ns
tpHL
Propagation Delay
(high to low transition); NOTE 1
1.5
2.7
ns
tPLZ, tPHZ
Disable Time
(active to high-impedance)
10
ns
tPZL, tPZH
Enable Time
(high-impedance to disable)
10
ns
tsk(o)
Output Skew; NOTE 2, 3
250
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
800
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
0.266
ps
tR / tF
Output Rise/Fall Time
0.525V to 0.975V
0.12
0.6
ns
odc
Output Duty Cycle
47
53
%
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