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| 型号： | ICS841003AKI-02T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 625 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC32 |
| 封装： | 5 X 5 MM, 0.75 MM HEIGHT, VFQFN-32 |
| 文件页数： | 1/17页 |
| 文件大小： | 343K |
| 代理商： | ICS841003AKI-02T |
FEMTOCLOCKS CRYSTAL-TO-0.7V DIFF/LVDS
FREQUENCY SYNTHESIZER FOR PCI EXPRESS
ICS841003I-02
IDT / ICS 0.7V DIFF/LVDS FREQUENCY SYNTHESIZER
1
ICS841003AKI-02 REV. A MARCH 19, 2007
PRELIMINARY
GENERAL DESCRIPTION
The ICS841003I-02 is a 3 differential output
Synthesizer designed to generate PCI Express or
10 Gigabit reference clock frequencies, and is a
member of the HiPerClock s family of high
performance clock solutions from IDT. Using a
31.25MHz, 26.041666MHz or 25MHz, 18pF parallel resonant
crystal, the following frequencies can be generated based on
the settings of 4 frequency select pins (DIV_SELA[1:0],
DIV_SELB[1:0]): 500MHz, 312.5MHz, 250MHz, 156.25MHz,
125MHz, and 100MHz. The 841003I-02 has 2 output banks,
Bank A with one 0.7V DIFF output pair and Bank B with two
differential LVDS output pairs.
The two banks have their own dedicated frequency select pins
and can be independently set for the frequencies mentioned
above. The ICS841003I-02 uses IDT’s 3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical
rms phase jitter, easily meeting PCI Express jitter requirements.
The ICS841003I-02 is packaged in a 32-pin VFQFN package.
FEATURES
Three differential outputs on two banks, Bank A with one
0.7V DIFF pair and Bank B with two LVDS output pairs
Using a 31.25MHz, 26.041666 or 25MHz crystal, supports
the following frequencies: 625MHz, 500MHz, 312.5MHz,
250MHz, 156.25MHz, 125MHz or 100MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz to 680MHz
RMS phase jitter @ 125MHz (1.875MHz - 20MHz):
0.54ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
0
1
0
1
Phase
Detector
VCO
490-680MHz
0 = ÷20 (default)
1 = ÷24
0 0
÷1
0 1
÷2 (default)
1 0
÷4
1 1
÷5
0 0
÷1
0 1
÷2 (default)
1 0
÷4
1 1
÷5
FB_DIV
OSC
QA0
nQA0
QB0
nQB0
QB1
nQB1
OEA
DIV_SELA[1:0]
DIV_SELB[1:0]
FB_DIV
MR
OEB
VCO_SEL
XTAL_SEL
IREF
REF_CLK
XTAL_IN
XTAL_OUT
Pullup
Pulldown:Pullup
Pullup
Pulldown
Pullup
Pulldown
Pulldown:Pullup
Pulldown
Pullup
0.7V DIFF
LVDS
BLOCK DIAGRAM
PIN ASSIGNMENT
24
23
22
21
20
19
18
17
QA0
nQA0
GND
QB0
nQB0
QB1
nQB1
VDDO_B
GND
XTAL_IN
XTAL_OUT
XTAL_SEL
VCO_SEL
MR
GND
nc
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
GND
FB_DIV
OEB
OEA
V
DDO
_
A
IREF
V
DD
V
DD
A
nc
V
DD
REF_CLK
ICS841003I-02
32-Lead VFQFN
5mm x 5mm x 0.75mm
package body
K Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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相关代理商/技术参数 |
参数描述 |
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